# US 6,723,615 B2 · Semiconductor device and method of fabricating the same

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- Number: US 6,723,615 B2
- Document ID: US6723615B2
- Status: Granted
- Kind: B2
- Application number: 10/197,870
- Filed: 2002-07-19
- Published: 2003-07-31
- Granted: 2004-04-20
- Earliest claimed: 2002-01-31
- Assignees: Renesas Technology Corp.
- Inventors: Shu Shimizu
- Web page: https://patentgrep.com/patent/US6723615B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 10/0147: {the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A highly reliable semiconductor device capable of preventing generation of a leakage current is provided. The semiconductor device comprises a silicon substrate having a main surface and including a trench formed on the main surface. The trench is defined by surfaces including a bottom surface, a side surface, continuous to the bottom surface, having first inclination with respect to the main surface, and an intermediate surface, formed between the main surface and the bottom surface, having second inclination smaller than the first inclination with respect to the main surface. The semiconductor device further comprises an n-type impurity region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a main surface and including a trench formed on said main surface, wherein
said trench is defined by surfaces including a bottom surface, a side surface, continuous to said bottom surface, having first inclination with respect to said main surface, an intermediate surface, formed between said main surface and said bottom surface, having second inclination smaller than said first inclination with respect to said main surface, and a surface of a portion of said main surface connected to said intermediate surface,
said semiconductor device further comprising an impurity region including a bottom surface having a depth from said main surface larger than the depth from said main surface to said intermediate surface, said impurity region extending to cover from said main surface to said intermediate surface, and
an insulation layer extending from said portion of said main surface to said bottom surface of said trench to fill said trench, wherein
said side and bottom surfaces of said trench are defined by a portion of said semiconductor substrate containing an impurity of a first conduction type and also contracting said impurity region, and
said impurity region contains an impurity of a second conduction type.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein said intermediate surface has a stepped shape.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein said intermediate surface has a portion substantially parallel to said main surface.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein a portion of said semiconductor substrate located in a vicinity of said intermediate surface is oxidized a larger number of times than a portion of said semiconductor substrate located between said side and bottom surfaces of said trench.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a gate insulator film formed on said main surface, a floating gate electrode formed on said gate insulator film, a dielectric film covering said floating gate electrode and said insulation layer, and a control gate electrode covering said dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising an interlayer isolation film formed on said main surface to have a contact hole reaching said impurity region and a conductive layer filling up said contact hole to be electrically connected to said impurity region, and also contacting said intermediate surface.

### Claim 7

A method of fabricating a semiconductor device, comprising steps of:
forming a first silicon oxide film on a main surface of a semiconductor substrate;
forming a polysilicon layer on said first silicon oxide film;
forming a mask layer including a first opening having a first opening diameter on said polysilicon layer;
selectively removing part of said polysilicon layer, part of said first silicon oxide film and part of said semiconductor substrate along said first opening through said mask layer serving as a mask thereby forming a second opening continuous to said first opening in said polysilicon layer, forming a third opening continuous to said second opening in said first silicon oxide film and forming a first cavity, defined by a side surface and a bottom surface, continuous to said third opening in said semiconductor substrate;
oxidizing the portion of said polysilicon layer defining said second opening and said side and bottom surfaces of said first cavity for forming a second silicon oxide film having a side portion and a bottom portion while forming a second cavity receiving said second silicon oxide film in said semiconductor substrate;
removing said bottom portion of said second silicon oxide film for exposing the bottom surface of said second cavity while leaving said side portion of said second silicon oxide film thereby forming a fourth opening, defined by said side portion, having an opening diameter smaller than said first opening diameter;
selectively removing part of said semiconductor substrate along said fourth opening through said side portion serving as a mask thereby forming a trench; and
oxidizing the surface of said trench.

### Claim 8 (depends on 7)

The method of fabricating a semiconductor device according to claim 7, wherein said step of forming said polysilicon layer includes a step of forming a strip-shaped conductive layer for defining a floating gate electrode,
said method further comprising a step of patterning said strip shaped conductive layer after forming said trench for forming said floating gate electrode.