Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process

A method of fabricating a vertical bipolar transistor, the method comprising the steps of:

• forming an extrinsic collector layer buried in a semiconductor substrate;
• forming an intrinsic collector on the extrinsic collector layer;
• forming a side insulation region surrounding an upper part of the intrinsic collector;
• forming an initial silicon nitride layer on the intrinsic collector and the side insulation region to define a window above a surface of the intrinsic collector;
• epitaxially growing a stack of layers of silicon and silicon-germanium on the surface of the intrinsic collector in the window and on the initial silicon nitride layer, thus forming an SiGe heterojunction base, and including epitaxially growing a first silicon layer, epitaxially growing a silicon-germanium layer on the first silicon layer, and epitaxially growing a second silicon layer on the silicon-germanium layer;
• and
• forming an emitter above the stack of layers.

A method of producing a base of a vertical bipolar transistor comprising a semiconductor region including an intrinsic collector surrounded by a side insulation region on an upper part of the intrinsic collector, the method comprising the steps of:

• forming a protective layer on the semiconductor region to define a window above a surface of the intrinsic collector;
• epitaxially growing a layer of silicon on the surface of the intrinsic collector in the window and on the protective layer;
• epitaxially growing a silicon-germanium layer on the silicon layer;
• and
• epitaxially growing a second silicon layer on the silicon-germanium layer.