# US 6,723,597 B2 · Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 6,723,597 B2
- Document ID: US6723597B2
- Status: Granted
- Kind: B2
- Application number: 10/191,833
- Filed: 2002-07-09
- Published: 2004-01-15
- Granted: 2004-04-20
- Earliest claimed: 2002-07-09
- Assignees: Micron Technology, Inc.
- Inventors: Todd R. Abbott; Mike Violette; Zhongze Wang; Jigish D. Trevidi
- Web page: https://patentgrep.com/patent/US6723597B2

## CPC

- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/12: {comprising a MOSFET load element}
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming, a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

## Claims

### Claim 1

A method of forming an SRAM memory cell, comprising:
forming a plurality of transistors above a semiconducting substrate;
forming a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and said transistors;
forming a dielectric layer above said BPSG layer, said dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0;
forming a plurality of openings in said dielectric layer and said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors; and
forming a conductive local interconnect in each of said openings.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming said BPSG layer comprises performing at least one of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process and an atomic layer deposition process.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness that ranges from approximately 150-200 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness such that an upper surface of said BPSG layer extends above an upper surface of one of said transistors by approximately 50-100 nm.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming a dielectric layer comprises performing at least one of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process and a spin-coating process.

### Claim 6 (depends on 1)

The method of claim 1, wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming a plurality of openings in said dielectric layer and said BPSG layer comprises performing at least one anisotropic etching process.

### Claim 8 (depends on 1)

The method of claim 1, wherein said conductive local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon.

### Claim 9

A method of forming an SRAM memory cell, comprising:
forming a plurality of transistors above a semiconducting substrate;
depositing a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and said transistors;
depositing a dielectric layer above said BPSG layer, said dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0;
etching a plurality of openings in said dielectric layer and said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors; and
forming a conductive local interconnect in each of said openings.

### Claim 10 (depends on 9)

The method of claim 9, wherein depositing said BPSG layer comprises performing at least one of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

### Claim 11 (depends on 9)

The method of claim 9, wherein depositing said BPSG layer comprises depositing said BPSG layer to a thickness that ranges from approximately 150-200 nm.

### Claim 12 (depends on 9)

The method of claim 9, wherein depositing said BPSG layer comprises depositing said BPSG layer to a thickness such that an upper surface of said BPSG layer extends above a top surface of one of said transistors by approximately 50-100 nm.

### Claim 13 (depends on 9)

The method of claim 9, wherein depositing a dielectric layer comprises performing at least one of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process and a spin-coating process.

### Claim 14 (depends on 9)

The method of claim 9, wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.

### Claim 15 (depends on 9)

The method of claim 9, wherein etching a plurality of openings in said dielectric layer and said BPSG layer comprises performing at least one anisotropic etching process.

### Claim 16 (depends on 9)

The method of claim 9, wherein said conductive local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon.

### Claim 17

A method of forming an SRAM memory cell, comprising:
forming a plurality of transistors above a semiconducting substrate;
forming a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
forming a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
forming a conductive local interconnect in each of said openings;
reducing a thickness of said BPSG, layer after said local interconnects are formed; and
forming a dielectric layer above said BPSG layer and between said conductive local interconnects.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming said BPSG layer comprises performing at least one of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness that ranges from approximately 500-1000 nm.

### Claim 20 (depends on 17)

The method of claim 17, wherein said dielectric layer is comprised of a material having a dielectric constant greater than approximately 6.0.

### Claim 21 (depends on 17)

The method of claim 17, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness such that an upper surface of said BPSG layer extends above a top surface of one of said transistors by approximately 50-100 nm.

### Claim 22 (depends on 17)

The method of claim 17, wherein forming a dielectric layer comprises performing at least one of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process and a spin-coating process.

### Claim 23 (depends on 17)

The method of claim 17, wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.

### Claim 24 (depends on 17)

The method of claim 17, wherein forming a plurality of openings comprises performing at least one anisotropic etching process.

### Claim 25 (depends on 17)

The method of claim 17, wherein reducing a thickness of said BPSG layer comprises performing at least one etching process to reduce said thickness of said BPSG layer.

### Claim 26 (depends on 17)

The method of claim 17, wherein said conductive local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon.

### Claim 27

A method of forming an integrated circuit device, comprising:
forming a plurality of transistors above a semiconducting substrate;
forming a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
forming a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
forming a conductive local interconnect in each of said openings;
reducing a thickness of said BPSG layer after said local interconnects are formed; and
forming a dielectric layer above said BPSG layer and between said conductive local interconnects.

### Claim 28 (depends on 27)

The method of claim 27, wherein forming said BPSG layer comprises performing at least one of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

### Claim 29 (depends on 27)

The method of claim 27, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness that ranges from approximately 500-1000 nm.

### Claim 30 (depends on 27)

The method of claim 27, wherein said dielectric layer is comprised of a material having a dielectric constant greater than approximately 6.0.

### Claim 31 (depends on 27)

The method of claim 27, wherein forming said BPSG layer comprises depositing said BPSG layer to a thickness such that an upper surface of said BPSG layer extends above a top surface of one of said transistors by approximately 50-100 nm.

### Claim 32 (depends on 27)

The method of claim 27, wherein forming a dielectric layer comprises performing at least one of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

### Claim 33 (depends on 27)

The method of claim 27, wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.

### Claim 34 (depends on 27)

The method of claim 27, wherein forming a plurality of openings comprises performing at least one anisotropic etching process.

### Claim 35 (depends on 27)

The method of claim 27, wherein reducing a thickness of said BPSG layer comprises performing at least one etching process to reduce said thickness of said BPSG layer.

### Claim 36 (depends on 27)

The method of claim 27, wherein said conductive local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon.

### Claim 37 (depends on 27)

The method of claim 27, wherein said integrated circuit device is an SRAM memory cell.

### Claim 38

A method of forming an SRAM memory cell, comprising:
forming a plurality of transistors above a semiconducting substrate;
depositing a layer comprised of boron phosphosilicate glass (BPSG) above said substrate and between said transistors;
etching a plurality of openings in said BPSG layer, each of said openings allowing contact to a doped region of one of said transistors;
forming a conductive local interconnect in each of said openings;
performing at least one etching process to reduce a thickness of said BPSG layer after said conductive local interconnects are formed; and
forming a dielectric layer above said BPSG layer and between said conductive local interconnects, said dielectric layer being comprised of a material having a dielectric constant greater than approximately 6.0.

### Claim 39 (depends on 38)

The method of claim 38, wherein depositing said BPSG layer comprises performing at least one of a chemical vapor deposition process and a plasma enhanced chemical vapor deposition process.

### Claim 40 (depends on 38)

The method of claim 38, wherein depositing said BPSG layer comprises depositing said BPSG layer to a thickness that ranges from approximately 500-1000 nm.

### Claim 41 (depends on 38)

The method of claim 38, wherein depositing said BPSG layer comprises depositing said BPSG layer to a thickness such that an upper surface of said BPSG layer extends above a top surface of one of said transistors by approximately 500-100 nm.

### Claim 42 (depends on 38)

The method of claim 38, wherein forming a dielectric layer comprises performing at least one of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process and a spin-coating process.

### Claim 43 (depends on 38)

The method of claim 38, wherein said dielectric layer is comprised of at least one of aluminum oxide, tantalum pentoxide, hafnium oxide and zirconium oxide.

### Claim 44 (depends on 38)

The method of claim 38, wherein etching a plurality of openings comprises performing at least one anisotropic etching process.

### Claim 45 (depends on 38)

The method of claim 38, wherein said conductive local interconnect is comprised of at least one of a metal, a metal alloy, tungsten, copper, aluminum and polysilicon.