# US 6,723,593 B1 · Deep submicron MOS transistor with increased threshold voltage

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- Number: US 6,723,593 B1
- Document ID: US6723593B1
- Status: Granted
- Kind: B1
- Application number: 10/185,960
- Filed: 2002-06-27
- Granted: 2004-04-20
- Earliest claimed: 2002-06-27
- Assignees: National Semiconductor Corporation
- Inventors: Gobi R. Padmanabhan; Visvamohan Yegnashankaran; Reda Razouk
- Web page: https://patentgrep.com/patent/US6723593B1

## CPC

- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.

## Claims

### Claim 1

A transistor formed in a semiconductor material of a first conductivity type, the transistor comprising:
spaced-apart source and drain regions of a second conductivity type formed in the semiconductor material,
the source region includes:
a first lightly-doped region,
a first heavily-doped region that is formed in the first lightly-doped region, and
a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region; and
the drain region includes:
a second lightly-doped region,
a third heavily-doped region that is formed in the second lightly-doped region, and
a fourth heavily-doped region that adjoins the second lightly-doped region and is spaced apart from the third heavily-doped region.

### Claim 2 (depends on 1)

The transistor of claim 1 and further comprising:
a channel region located between the source and drain regions;
a gate oxide layer formed over the channel region, and
a channel gate formed on the gate oxide layer over the channel region, the channel gate having side walls.

### Claim 3 (depends on 2)

The transistor of claim 2 and further comprising:
a side wall spacer adjoining the side walls of the channel gate; and
a first outer gate adjoining the side wall spacer formed over the first heavily-doped region.

### Claim 4 (depends on 3)

The transistor of claim 3 wherein the first outer gate is also formed over the third heavily-doped region.

### Claim 5 (depends on 3)

The transistor of claim 3 and further comprising a second outer gate adjoining the side wall spacer formed over the third heavily-doped region, the first outer gate and the second outer gate being electrically isolated from each other.

### Claim 6 (depends on 5)

The transistor of claim 5 wherein the first outer gate and the second outer gate are electrically connected together.

### Claim 7

A method of using a MOS transistor formed in a semiconductor material of a first conductivity type,
the transistor having:
spaced-apart source and drain regions of a second conductivity type formed in the semiconductor material,
the source region includes:
a first lightly-doped region,
a first heavily-doped region that is formed in the first lightly-doped region, and
a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region; and
the drain region includes:
a second lightly-doped region,
a third heavily-doped region that is formed in the second lightly-doped region, and
a fourth heavily-doped region that adjoins the second lightly-doped region and is spaced apart from the third heavily-doped region;
a channel region located between the source and drain regions;
a gate oxide layer formed over the channel region, and
a channel gate formed on the gate oxide layer over the channel region, the channel gate having side walls;
ground applied to the second heavily-doped region;
a first positive voltage applied to the fourth heavily-doped region; and
a second positive voltage applied to the channel gate, the second positive voltage being equal to or greater than a voltage required to invert the channel region of the MOS transistor;
the transistor being biased off by:
inducing a first potential in the first heavily-doped region that is substantially equal to ground, and
inducing a second potential in the third heavily-doped region that is substantially equal to ground.

### Claim 8 (depends on 7)

The method of claim 7 wherein the MOS transistor is biased from off to on by inducing
a third potential in the first heavily-doped region that is equal to or greater than a minimum potential required to form a channel, and
a fourth potential on the third heavily-doped region that is equal to or greater than a minimum potential required to form a channel, the fourth potential being greater than a voltage required to invert the channel region of the MOS transistor.

### Claim 9 (depends on 8)

The method of claim 8 wherein the third potential is equal to the fourth potential.

### Claim 10 (depends on 8)

The method of claim 8 wherein the third potential is less than the fourth potential.

### Claim 11 (depends on 8)

The method of claim 8 wherein the third potential is greater than the fourth potential.

### Claim 12 (depends on 8)

The method of claim 8 wherein the MOS transistor is biased from on to off by inducing a potential substantially equal to ground on the third heavily-doped region.

### Claim 13 (depends on 8)

The method of claim 8 wherein the MOS transistor is biased from on to off by inducing a potential substantially equal to ground on the first heavily-doped region.

### Claim 14

A method of forming a MOS transistor in a semiconductor material of a first conductivity type, the transistor having a layer of gate oxide formed over the semiconductor material, and a gate formed on the layer of gate oxide over a region of the semiconductor material, the method comprising the steps of:
implanting the semiconductor material with a dopant of the second conductivity type to form a lightly-doped source region and a lightly-doped drain region;
forming a side wall spacer that adjoins the side walls of the gate; and
forming an outer gate on the layer of gate oxide to adjoin the side wall spacer over the lightly-doped source region and the lightly-doped drain region.

### Claim 15 (depends on 14)

The method of claim 14 and further comprising the steps of:
implanting the lightly-doped source region to form to form a heavily-doped source pocket region of the second conductivity type in the lightly-doped source region under the outer gate; and
implanting the lightly-doped drain region to form to form a heavily-doped drain pocket region of the second conductivity type in the lightly-doped drain region under the outer gate.

### Claim 16 (depends on 15)

The method of claim 15 and further comprising the step of forming:
a heavily-doped source region of the second conductivity type that adjoins the lightly-doped source region and is spaced away from the source pocket region, and
a heavily-doped drain region of the second conductivity type that adjoins the lightly-doped drain region and is spaced away from the drain pocket region.

### Claim 17 (depends on 14)

The method of claim 14 and further comprising the steps of:
etching the outer gate to form a first outer gate and a second outer gate that is electrically isolated from the first outer gate;
implanting the lightly-doped source region to form to form a heavily-doped source pocket region of the second conductivity type in the lightly-doped source region under the side wall gate; and
implanting the lightly-doped drain region to form to form a heavily-doped drain pocket region of the second conductivity type in the lightly-doped drain region under the side wall gate.

### Claim 18 (depends on 17)

The method of claim 17 and further comprising the step of forming:
a heavily-doped source region of the second conductivity type that adjoins the lightly-doped source region and is spaced away from the source pocket region, and
a heavily-doped drain region of the second conductivity type that adjoins the lightly-doped drain region and is spaced away from the drain pocket region.

### Claim 19

A transistor formed in a semiconductor material of a first conductivity type, the transistor comprising:
spaced-apart diffusion regions of a second conductivity type formed in the semiconductor material,
a diffusion region of the spaced-apart diffusion regions having:
a first lightly-doped region,
a first heavily-doped region that is formed in the first lightly-doped region, and
a second heavily-doped region that adjoins the first lightly-doped region and is spaced apart from the first heavily-doped region;
a channel region located between the source and drain regions;
a gate oxide layer formed over the channel region; and
a center gate formed on the gate oxide layer over the channel region, the center gate having side walls.

### Claim 20 (depends on 19)

The transistor of claim 19 and further comprising:
a side wall spacer adjoining the side walls of the center gate; and
an outer gate adjoining the side wall spacer formed over the first heavily-doped region.