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US 6,723,592 B2Granted
Method of fabricating an X-ray detector array element
AssigneeHannstar Display Corp.
InventorPo-Sheng Shih
Life of this patent
Estimating the term…
Abstract
A method of fabricating an X-ray detector array element. The method decreases consumption of masks during photolithography. A first mask defines a gate line on a substrate. A second mask defines a semiconducting island on a gate insulation layer. A third mask defines a common line and a data line on the gate insulation layer, and source and drain electrodes are simultaneously formed on the semiconducting island, thereby obtaining a TFT structure. A fourth mask defines a first conductive layer on a planarization layer. A fifth mask defines first and second via holes penetrating the planarization layer. A sixth mask defines a third conductive layer, a fourth conductive layer, and a first opening.
Claims20
A method of fabricating an X-ray detector array, comprising:
- providing a substrate having a capacitor area and a transistor area;
- forming a gate line extending transversely on the substrate, wherein the gate line includes a gate electrode in the transistor area;
- forming a gate insulation layer on the gate line, the gate electrode, and the substrate;
- forming a semiconducting island on the gate insulation layer in the transistor area;
- forming a common line and a data line extending longitudinally on the gate insulation layer, and forming a source electrode and a drain electrode on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects to the data line;
- forming a planarization layer on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line;
- forming a first conductive layer on the planarization layer in the capacitor area;
- forming a dielectric layer on the first conductive layer and the planarization layer;
- forming a first via hole and a second via hole penetrating the dielectric layer and the planarization layer, wherein the first via hole exposes a surface of the source electrode, and the second via hole exposes part of a surface of the first conductive layer and part of a surface of the common line;
- forming a conformal second conductive layer on the dielectric layer, an interior surrounding surface of the first via hole, and an interior surrounding surface of the second via hole;
- and
- removing part of the second conductive layer to form a third conductive layer, a fourth conductive layer, and a first opening, wherein the third conductive layer is isolated from the fourth conductive layer by the first opening;
- wherein the third conductive layer electrically connects to the source electrode;
- wherein the first conductive layer electrically connects to the common line by the fourth conductive layer;
- and
- wherein a storage capacitor structure is composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area.
13 more elements
A method of fabricating an X-ray detector array, comprising:
- providing a substrate having a capacitor area and a transistor area;
- forming a gate line extending transversely on the substrate, wherein the gate line includes a gate electrode in the transistor area;
- forming a gate insulation layer on the gate line, the gate electrode, and the substrate;
- forming a semiconducting island on the gate insulation layer in the transistor area;
- forming a common line and a data line extending longitudinally on the gate insulation layer, and forming a source electrode and a drain electrode on the semiconductor island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects to the data line;
- forming a planarization layer on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line;
- forming a first conductive layer on the planarization layer in the capacitor area, wherein the first conductive layer has a first opening to expose the planarization layer above the common line;
- forming a dielectric layer on the first conductive layer and the planarization layer;
- forming a first via hole and a second via hole penetrating the dielectric layer and the planarization layer, wherein the first via hole exposes a surface of the source electrode, the second via hole exposes part of a surface of the first conductive layer and part of a surface of the common line, and the second via hole and the first opening have an overlap;
- forming a conformal second conductive layer on the dielectric layer, an interior surrounding surface of the first via hole, and an interior surrounding surface of the second via hole;
- and
- removing part of the second conductive layer to form a third conductive layer, a fourth conductive layer, and a second opening, wherein the third conductive layer is isolated from the fourth conductive layer by the second opening;
- wherein the third conductive layer electrically connects to the source electrode;
- wherein the first conductive layer electrically connects to the common line by the fourth conductive layer;
- and
- wherein a storage capacitor structure is composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area.
13 more elements
A method of fabricating an X-ray detector array, used to decrease consumption of masks during photolithography, comprising:
- providing a substrate having a capacitor area and a transistor area;
- using a first mask to form a gate line transversely extending on the substrate by photolithography, wherein the gate line includes a gate electrode in the transistor area;
- forming a gate insulation layer on the gate line, the gate electrode, and the substrate;
- using a second mask to form a semiconducting island on the gate insulation layer in the transistor area by photolithography;
- using a third mask to form a common line and a data line longitudinally extending on the gate insulation layer by photolithography, and forming a source electrode and a drain electrode on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects to the data line;
- forming a planarization layer on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line;
- using a fourth mask to form a first conductive layer on the planarization layer in the capacitor area by photolithography;
- forming a dielectric layer on the first conductive layer and the planarization layer;
- using a fifth mask to form a first via hole and a second via hole penetrating the dielectric layer and the planarization layer by photolithography, wherein the first via hole exposes a surface of the source electrode, and the second via hole exposes part of a surface of the first conductive layer and part of a surface of the common line;
- forming a conformal second conductive layer on the dielectric layer, an interior surrounding surface of the first via hole, and an interior surrounding surface of the second via hole;
- and
- using a sixth mask to remove part of the second conductive layer to form a third conductive layer, a fourth conductive layer, and a first opening by photolithography, wherein the third conductive layer is isolated from the fourth conductive layer by the first opening;
- wherein the third conductive layer electrically connects to the source electrode;
- wherein the first conductive layer electrically connects to the common line by the fourth conductive layer;
- and
- wherein a storage capacitor structure is composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area.
13 more elements
Dependencies are inferred from the claim text.