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US 6,721,380 B2Granted
Fully differential CMOS phase-locked loop
AssigneeBroadcom Corporation
InventorsArmond Hairapetian, Jun Cao, Afshin Momtaz
Life of this patent
Estimating the term…
Abstract
The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.
Claims26
A differential phase-locked loop comprising:
- a differential detector configured to receive a pair of input signals and a pair of reference signals and to provide a pair of detector output signals indicative of a difference between the pair of input signals and the pair of reference signals;
- a differential signal filter coupled to the detector and configured to receive the pair of detector output signals and to provide a pair of control signals;
- and
- a differential voltage controlled oscillator coupled to the signal filter and configured to receive the pair of control signals and to provide a pair of oscillator signals which is adjustable based on the pair of control signals, the pair of oscillator signals is fed back to the detector as the pair of input signals;
- wherein the differential detector, the differential signal filter, and the differential voltage controlled oscillator are connected to one another in a fully differential manner.
2 more elements
A phase-locked loop comprising:
- a detector configured to receive a pair of differential input signals and a pair of differential reference signals and to provide a pair of differential detector output signals indicative of a difference between the pair of differential input signals and the pair of differential reference signals;
- a Gm cell circuit coupled to the detector and configured to receive the pair of differential detector output signals and to provide a pair of differential current output signals;
- a signal filter coupled to the Gm cell circuit and configured to receive the pair of differential current output signals and to provide a pair of differential control signals;
- and
- a voltage controlled oscillator coupled to the signal filter and configured to receive the pair of differential control signals and to provide a pair of differential oscillator signals which is adjustable based on the pair of differential control signals, the pair of differential oscillator signals is fed back to the detector as the pair of differential input signals;
- wherein the detector, the Gm cell circuit, the signal filter, and the voltage controlled oscillator are each implemented using CMOS logic.
3 more elements
A phase-locked loop comprising:
- a detector configured to receive a pair of input signals and a pair of reference signals and to provide a pair of detector output signals indicative of a difference between the pair of input signals and the pair of reference signals;
- a Gm cell circuit coupled to the detector and configured to receive the pair of detector output signals and to provide a pair of current output signals;
- a signal filter coupled to the Gm cell circuit and configured to receive the pair of current output signals and to provide a pair of control signals;
- a voltage controlled oscillator coupled to the signal filter and configured to receive the pair of control signals and to provide a pair of oscillator signals which is adjustable based on the pair of control signals;
- and
- a divider circuit coupled to the voltage controlled oscillator and configured to receive the pair of oscillator signals and to provide a divided version of the pair of oscillator signals to be fed to the detector as the pair of input signals;
- wherein the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit are connected to one another in a fully differential manner;
- and
- wherein the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit are implemented using C3MOS logic.
6 more elements
A method for implementing a phase-locked loop, comprising:
- providing a pair of differential input signals and a pair of differential reference signals to a detector;
- providing a pair of differential detector output signals from the detector as input to a signal filter;
- providing a pair of differential control signals from the signal filter as input to a voltage controlled oscillator;
- and
- providing a pair of differential oscillator signals from the voltage controlled oscillator as the pair of differential input signals to the detector.
2 more elements
A method for implementing a phase-locked loop, comprising:
- providing a pair of differential input signals and a pair of differential reference signals to a detector;
- providing a pair of differential detector output signals from the detector as input to a Gm cell circuit;
- providing a pair of differential current output signals from the Gm cell circuit as input to a signal filter;
- providing a pair of differential control signals from the signal filter as input to a voltage controlled oscillator;
- providing a pair of differential oscillator signals from the voltage controlled oscillator as input to a divider circuit;
- providing a divided version of the pair of differential oscillator signals from the divider circuit as the pair of differential input signals to the detector;
- and
- implementing the detector, the Gm cell circuit, the signal filter, the voltage controlled oscillator and the divider circuit using C3MOS logic.
5 more elements
Dependencies are inferred from the claim text.