DAC/Driver waveform generator with phase lock rise time control
AssigneeInternational Business Machines Corporation
InventorsHayden Clay Cranford, Jr., Raymond Paul Rizzo
Life of this patent
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Abstract
A system that generates data waveforms for transmission on a communications network includes a series of sequentially over sampled and switch current sources whose timings are locked to a master delay line and replicas thereof. The master delay is configured as a ring oscillator with its frequency looked to a precise clock reference. The clock controls the rise and fall of the data waveforms thus making them immune to variations in semiconductor processes used to implement the system.
Claims12
A waveform generator generating signals for use with high speed (100 Mbps through gigabits) data transmission including;
- a delay phase lock loop generator being responsive to a reference frequency and operatively generating control signals at precisely spaced time intervals, said delay phase lock loop generator including a master delay line with predrivers having double ended inputs and single ended output;
- at least one replica delay line receiving data signals and using said control signals to advance the data signals there-through;
- and
- a conversion circuit arrangement being responsive to convert signals outputted from said at least one replica delay line.
A waveform generator including:
- a delay phase lock loop generator being responsive to a reference frequency and operatively generating control signals at precisely spaced time intervals, said delay phase look loop generator including a delay line with differential to single ended predrivers;
- and
- at least one replica delay line, including a delay line with differential to single ended predrivers, receiving data signals and using said control signals to advance the data signals there-through.
Dependencies are inferred from the claim text.