Method and circuit configuration for resynchronizing a clock signal

Abstract

A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal. The invention also includes a circuit configuration for resynchronizing a clock signal, including a programmable digital frequency divider for dividing a first clock signal to produce second clock signal, a digital measuring circuit, connected to the frequency divider, for measuring the second clock signal and generating an output signal, and a digital control circuit, connected to the frequency divider and to the measuring circuit, for evaluating the output signal from the measuring circuit and for adjusting the frequency divider.

Dependencies are inferred from the claim text.