One sample per symbol high rate programmable parallel architecture for digital demodulation

A method for acquiring information signals from an analog transmission signal, the method comprising steps of:

• receiving the analog transmission signal;
• mixing the analog transmission signal to produce a first analog signal and a second analog signal;
• digitizing the first analog signal to provide a first stream of digitized signals (I stream);
• digitizing the second analog signal to provide a second stream of digitized signals (Q stream);
• demultiplexing the I and Q streams of digitized signals to an array of programmable demodulators, the array of programmable demodulators having a first programmable demodulator, wherein each of the programmable demodulators further comprises an application specific integrated circuit (ASIC), comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals.

A method of high rate demodulation of a series of modulated analog signals, the method comprising steps of:

• acquiring and digitizing the series of modulated analog signals;
• providing parallel programmable demodulation of the digitized series of modulated analog signals;
• providing a plurality of parallel demodulated data;
• and
• reorganizing the demodulated data by providing a plurality of samples of the plurality of parallel demodulated data to a timing interface, a data processor, and a phase reference interface;
• sequencing the plurality of parallel demodulated data provided to the data processor according to a plurality of controls provided by a phase reference interface;
• controlling timing of at least one of a plurality of demodulator application specific integrated circuits (ASICs) responsive to the plurality of samples of the plurality of parallel demodulated data;
• and
• providing an output of at least one of the plurality of demodulator ASICS to an analog to digital converter.

A high speed demodulator system comprising:

• an analog to digital converter (ADC);
• a high speed demultiplexer connected to an output of the ADC;
• a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer comprising an array of programmable application specific integrated circuits (ASICs), wherein each ASIC further comprises an integrated circuit, comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals;
• a timing interface connected to the bank of parallel programmable demodulators;
• and
• a phase reference interface connected to the bank of parallel programmable demodulators and a data processor.