US 6,721,317 B2 · Switch-based scalable performance computer memory architecture

Abstract

Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system iops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol. The computer system achieves separation of control and data paths using a modified switch and standard host adapter hardware and host driver software. In addition, a two party protocol such as the Fibre Channel protocol is not violated.

Claims6

Dependent claims

A data switch, comprising;

a memory unit for storing frame header substitution information, wherein the frame header substitution information comprises a substitute destination address;
a plurality of ports, wherein each of the plurality of ports is adapted for coupling to a transmission medium;
an array of switching elements for selectively coupling the plurality of ports to one another;
a switch matrix control unit coupled to receive routing information from the plurality of ports and configured to control the array of switching elements dependent upon the routing information;
wherein the data switch is configured to receive frame header substitution information on one of the plurality of ports and to store the frame header substitution information within the memory unit;
and
wherein the data switch is further configured to:
(i) receive a data frame on a port other than the port on which the frame header substitution information was received, wherein the data frame comprises header information including a destination address, (ii) replace the header information of the data frame with the substitute header information stored within the memory unit such that the substitute destination address becomes a new destination address, and (iii) provide the new destination address to the switch matrix control unit as the routing information.

5 more elements

Dependencies are inferred from the claim text.

Switch-based scalable performance computer memory architecture

Life of this patent

Switch-based scalable performance computer memory architecture

Life of this patent

Abstract

Claims6