# US 6,721,310 B2 · Multiport non-blocking high capacity ATM and packet switch

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- Number: US 6,721,310 B2
- Document ID: US6721310B2
- Status: Granted
- Kind: B2
- Application number: 10/000,272
- Filed: 2001-11-02
- Published: 2003-05-29
- Granted: 2004-04-13
- Earliest claimed: 2001-11-02
- Assignees: TranSwitch Corporation
- Inventors: Zheng Liu; Jiu An; Terry Xian; Ronald P. Novick
- Web page: https://patentgrep.com/patent/US6721310B2

## CPC

- G01N 33/586: {Liposomes, microcapsules or cells}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)

## Abstract

A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8×8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.

## Claims

### Claim 1

A multiport non-blocking high capacity ATM and packet switch comprising:
a) a single chip;
b) an internal unidirectional time slotted looped bus located on said chip;
c) a bus controller located on said chip and coupled to said bus;
d) a microprocessor interface on said chip and coupled to said bus; and
e) a plurality of switch ports on said chip and coupled to said bus, wherein each of said switch ports includes a UTOPIA interface wherein
each port includes a full duplex interface.

### Claim 2 (depends on 1)

A switch according to claim 1, wherein:
said bus controller continuously generates fixed size time slots to said bus.

### Claim 3 (depends on 1)

A switch according to claim 1, wherein:
said bus controller performs a medium access control protocol for prioritized fair access among all of said switch ports.

### Claim 4 (depends on 1)

A switch according to claim 1, wherein:
said full duplex interface includes a plurality of ingress FIFO buffers and a plurality of egress FIFO queues.

### Claim 5 (depends on 4)

A switch according to claim 4, wherein:
each port includes a counter array coupled to said ingress FIFO buffers and to said UTOPIA interface, said counter arrays being adapted to control UTOPIA input depending on the contents of said ingress FIFO buffers.

### Claim 6 (depends on 4)

A switch according to claim 4, further comprising:
f) a congestion bitmap on said chip and coupled to said UTOPIA interface of each of said ports, wherein
each port includes a congestion indication means coupled to each of said egress FIFO queues and to said congestion bitmap for indicating a state of congestion in each of said egress FIFO queues, said congestion bitmap being adapted to control UTOPIA input of said UTOPIA interfaces.

### Claim 7 (depends on 1)

A switch according to claim 1, wherein:
said UTOPIA interface are 16-bit mode UTOPIA Level 2 compliant interfaces.

### Claim 8 (depends on 1)

A switch according to claim 1, wherein:
data is transferred over said bus in cells of 80 bytes.

### Claim 9 (depends on 8)

A switch according to claim 8, wherein:
the first 16 bytes of each cell is overhead used for bus access control, address/map fields, and high-speed inter-block communication, and
the remaining 64 bytes are used to carry payload.

### Claim 10 (depends on 1)

A switch according to claim 1, wherein:
said switch is capable of switching variable length packets.

### Claim 11

A multiport non-blocking high capacity ATM and packet switch comprising:
a) an internal bus;
b) a bus controller coupled to said bus;
c) a microprocessor interface coupled to said bus;
d) a plurality of switch ports coupled to said bus, wherein each of said switch ports includes a UTOPIA interface and one of an ingress buffer and an egress queue; and
e) congestion control means coupled to each of said one of an ingress buffer and an egress queue and to at least one of said UTOPIA interfaces such that said at least one of said UTOPIA interfaces is directed to stop accepting data when one of said one of an ingress buffer and an egress queue is congested, wherein
each of said switch ports has an ingress buffer,
said congestion control means is coupled to each of said ingress buffers and each of said UTOPIA interfaces such that a UTOPIA interface associated with a particular switch port is directed to stop accepting data when said ingress buffer associated with said particular switch port is congested.

### Claim 12 (depends on 11)

A multiport non-blocking high capacity ATM and packet switch according to claim 11, wherein:
each of said switch ports has an egress queue,
said congestion control means is coupled to each of said egress queues and each of said UTOPIA interfaces such that a UTOPIA interface is directed to stop accepting data destined for an egress queue which is congested.

### Claim 13 (depends on 11)

A multiport non-blocking high capacity ATM and packet switch according to claim 11, wherein:
said congestion control means includes an array of counters.

### Claim 14 (depends on 11)

A multiport non-blocking high capacity ATM and packet switch according to claim 11, wherein:
said congestion control means includes a congestion bitmap.

### Claim 15 (depends on 11)

A multiport non-blocking high capacity ATM and packet switch according to claim 11, wherein:
said switch is capable of switching variable length packets.

### Claim 16

A multiport non-blocking high capacity ATM and packet switch comprising:
a) an internal bus;
b) a bus controller coupled to said bus;
c) a microprocessor interface coupled to said bus;
d) a plurality of switch ports coupled to said bus, wherein each of said switch ports includes a UTOPIA interface and one of an ingress buffer and an egress queue: and
e) congestion control means coupled to each of said one of an ingress buffer and an egress queue and to at least one of said UTOPIA interfaces such that said at least one of said UTOPIA interfaces is directed to stop accepting data when one of said one of an ingress buffer and an egress queue is congested, wherein
each of said switch ports has an egress queue,
said congestion control means is coupled to each of said egress queues and each of said UTOPIA interfaces such that a UTOPIA interface is directed to stop accepting data destined for an egress queue which is congested.