US 6,721,295 B1 · Triple data system for high data rate communication systems

Abstract

A slot-aligned IQ data buffer scheme has a third buffer that allows a processing engine to slide the selection of a vector to be processed so that it aligns with the framing of the data. This is particularly advantageous for CDMA and WCDMA systems where there are overlaying coded data streams, each with its own frame timing, since data is processed cleanly at boundaries in the data such that the processing hardware can be minimized. A first level of muxing selects a pair of buffers having the data to be processed from among three buffers. A second level of muxing selects the sample number required. The third level of muxing selects the correct chips for the alignment of the slot. The third stage is implemented with a barrel shifter to minimize hardware generally associated with use of multiplexing.

Claims18

Dependent claims

A slot-aligned IQ data buffer for high bit rate communication systems comprising:

a first data buffer;
a second data buffer;
a third data buffer;
a first data multiplexer in communication with the first data buffer, the second data buffer and the third data buffer and operational to select a pair of data buffers in response to a desired time window;
a second data multiplexer in communication with the first data multiplexer and operational to select a single on-time data sample in response to a desired sample number;
a third data multiplexer in communication with the first data multiplexer and operational to select a single late-time data sample in response to a desired sample number;
a first barrel shifter in communication with the second data multiplexer and operational to select chips that are slot-aligned with incoming frames of data to generate slot-aligned on-time data samples;
and
a second barrel shifter in communication with the third data multiplexer and operational to select chips that are slot-aligned with incoming frames of data to generate slot-aligned late-time data samples.

6 more elements

Dependencies are inferred from the claim text.

Triple data system for high data rate communication systems

Life of this patent

Triple data system for high data rate communication systems

Life of this patent

Abstract

Claims18