Method and apparatus for using SDRAM to read and write data without latency
AssigneeNetwork Equipment Technologies, Inc.
InventorPhilip D. Cole
Life of this patent
Estimating the term…
Abstract
An apparatus and method are provided for transmitting data using synchronous dynamic random access memory (SDRAM). In example, the method includes writes data using a first set of SDRAM banks. Data is written using a second set of SDRAM banks, wherein the first set of SDRAM banks and the second set of SDRAM banks write interleaved, Data is read using a third set of SDRAM banks. Data is read using a fourth set of SDRAM banks, wherein the fourth set of SDRAM banks and the third set of SDRAM banks read interleaved.
Claims18
A method of using synchronous dynamic random access memory (SDRAM) to transmit data, the method comprising:
- writing data using a first even addressed SDRAM bank;
- writing data using a second even addressed SDRAM bank,
- wherein the first even addressed SDRAM bank and the second even addressed SDRAM bank write in parallel;
- writing data using a first odd addressed SDRAM bank,
- wherein the first odd addressed SDRAM bank and the first even addressed SDRAM bank write interleaved;
- and
- writing data using a second odd addressed SDRAM bank,
- wherein the second odd addressed SDRAM bank and the first odd addressed SDRAM bank write in parallel, and wherein the second odd addressed SDRAM bank and the second even addressed SDRAM bank write interleaved.
An apparatus for transmitting data using synchronous dynamic random access memory (SDRAM), the apparatus comprising:
- a first even addressed SDRAM bank;
- a second even addressed SDRAM bank, wherein the first even addressed SDRAM bank and the second even addressed SDRAM bank are configured to write in parallel;
- a first odd addressed SDRAM bank, wherein the first add addressed SDRAM bank and the first even addressed SDRAM bank are configured to write interleaved;
- and
- a second odd addressed SDRAM bank, wherein the second odd addressed SDRAM bank and the first odd addressed SDRAM bank are configured to write in parallel, and wherein the second odd addressed SDRAM bank and the second even addressed SDRAM bank are configured to write interleaved.
A computer readable medium carrying one or more sequences of one or more instructions for transmitting data using synchronous dynamic random access memory (SDRAM), the one or more sequences of one or more instructions including instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of:
- writing data using a first even addressed SDRAM bank;
- writing data using a second even addressed SDRAM bank, wherein the first even addressed SDRAM bank and the second even addressed SDRAM bank write in parallel;
- writing data using a first odd addressed SDRAM bank, wherein the first odd addressed SDRAM bank and the first even addressed SDRAM bank write interleaved;
- and
- writing data using a second odd addressed SDRAM bank, wherein the second odd addressed SDRAM bank and the first odd addressed SDRAM bank write in parallel, and wherein the second odd addressed SDRAM bank and the second even addressed SDRAM bank write interleaved.
Dependencies are inferred from the claim text.