# US 6,721,226 B2 · Methods and systems for reducing heat flux in memory systems

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- Number: US 6,721,226 B2
- Document ID: US6721226B2
- Status: Granted
- Kind: B2
- Application number: 10/361,109
- Filed: 2003-02-07
- Published: 2003-06-26
- Granted: 2004-04-13
- Earliest claimed: 2000-10-10
- Assignees: Rambus Inc.
- Inventors: Steven C. Woo; Craig E. Hampel
- Web page: https://patentgrep.com/patent/US6721226B2

## CPC

- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.

## Claims

### Claim 1

A memory module comprising:
one or more faces;
multiple channels on one or more of the faces;
multiple memory devices on each channel, the memory devices being configured for operation in lock-step; and
device IDs for each device, the device IDs being arranged in a manner to reduce heat flux associated with the memory module.

### Claim 2 (depends on 1)

The memory module of claim 1, wherein the memory devices are disposed on each of the faces of the module.

### Claim 3 (depends on 1)

The memory module of claim 1, wherein corresponding devices on each channel are assigned the same device ID.

### Claim 4 (depends on 1)

The memory module of claim 1, wherein corresponding devices on each channel are not assigned the same device ID.

### Claim 5 (depends on 1)

The memory module of claim 1, wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged to maximize the physical distance between corresponding devices.

### Claim 6 (depends on 5)

The memory module of claim 5, wherein the physical distance between corresponding devices is maximized on a per face basis, where corresponding devices can appear on the same face of the module.

### Claim 7 (depends on 1)

The memory module of claim 1 wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged so that corresponding devices are on different faces of the module.

### Claim 8 (depends on 1)

The memory module of claim 1, wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged: (1) to maximize the physical distance between corresponding devices; and (2) so that corresponding devices are on different faces of the module.

### Claim 9 (depends on 8)

The memory module of claim 8, wherein all corresponding devices are on different faces of the module.

### Claim 10 (depends on 1)

The memory module of claim 1, wherein the module comprises at least four channels.

### Claim 11

A memory system comprising:
one or more memory modules, each of which comprising:
one or more faces;
multiple channels on one or more of the faces; and
multiple memory devices on each channel, the memory devices being configured for operation in lock-step; and
a memory controller operably connected with the one or more memory modules, the memory controller being configured to assign device IDs for each device, the device IDs being arranged in a manner to reduce heat flux associated with the one or more memory modules.

### Claim 12 (depends on 11)

The memory system of claim 11 comprising multiple memory modules, wherein corresponding devices on different channels share the same device ID, at least some of the corresponding devices be disposed on different modules.

### Claim 13 (depends on 11)

The memory system of claim 11, wherein corresponding devices that are operated in lock step on each channel are assigned the same device ID.

### Claim 14 (depends on 11)

The memory system of claim 11, wherein corresponding devices that are operated in lock step on each channel are not assigned the same device ID.

### Claim 15 (depends on 11)

The memory system of claim 11, wherein corresponding devices that are operated in lock step on each channel are not assigned the same device ID, the memory controller being configured to manage which memory devices are corresponding devices.

### Claim 16

A memory module comprising:
one or more faces;
multiple channels on one or more of the faces;
multiple DRAM devices on each channel, the DRAM devices being configured for operation in lock-step; and
device IDs for each DRAM device, corresponding DRAM devices on different channels having the same device ID, the device IDs being arranged in a manner to reduce heat flux associated with the memory module.

### Claim 17 (depends on 16)

The memory module of claim 16, comprising two or more DRAM devices on each channel.

### Claim 18 (depends on 16)

The memory module of claim 16, comprising four or more DRAM devices on each channel.

### Claim 19 (depends on 16)

The memory module of claim 16, comprising four or more DRAM devices on each face.

### Claim 20 (depends on 16)

The memory module of claim 16, comprising eight or more DRAM devices on each module.

### Claim 21 (depends on 16)

The memory module of claim 16, comprising DRAM devices on each face.

### Claim 22

A memory system comprising:
one or more memory modules, each of which comprising:
one or more faces;
multiple channels on one or more of the faces; and
multiple DRAM devices on each channel, the DRAM devices being configured for operation in lock-step; and
a memory controller operably connected with the one or more memory modules, the memory controller being configured to assign device IDs for each DRAM device, corresponding DRAM devices on different channels having the same device ID, the device IDs being arranged in a manner to reduce heat flux associated with the one or more memory module.

### Claim 23

A method comprising:
providing one or more memory modules each comprising one or more faces, multiple channels on one or more of the faces, multiple memory devices on each channel, the memory devices being configured for operation in lock-step; and
assigning device IDs for each device, the device IDs being arranged in a manner to reduce heat flux associated with the one or more memory modules.

### Claim 24 (depends on 23)

The method of claim 23, wherein the memory devices are disposed on each of the faces for at least some of the modules.

### Claim 25 (depends on 23)

The method of claim 23, wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged to maximize the physical distance between corresponding devices.

### Claim 26 (depends on 25)

The method of claim 25, wherein the physical distance between corresponding devices is maximized on a per face basis, where corresponding devices can appear on the same face of the module.

### Claim 27 (depends on 23)

The method of claim 23, wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged so that corresponding devices are on different faces of the module or on different modules.

### Claim 28 (depends on 23)

The method of claim 23, wherein corresponding devices on each channel are assigned the same device ID, the device IDs being arranged: (1) to maximize the physical distance between corresponding devices; and (2) so that corresponding devices are on different faces of a module or on different modules.

### Claim 29 (depends on 28)

The method of claim 28, wherein all corresponding devices are on different faces of a module.

### Claim 30 (depends on 23)

The method of claim 23, wherein said assigning is performed by a memory controller that is operably connected to the one or more memory modules.

### Claim 31 (depends on 23)

The method of claim 23, wherein said assigning is performed by a memory controller that is operably connected to the one or more memory modules, said assigning taking place at initialization time.

### Claim 32 (depends on 23)

The method of claim 23, wherein said assigning is performed when the one or more memory modules are manufactured.

### Claim 33 (depends on 23)

The method of claim 23 further comprising operating the one or more memory modules in lock-step.

### Claim 34

A method comprising:
providing one or more memory modules each comprising one or more faces, multiple channels on one or more of the faces, multiple DRAM devices on each channel, the DRAM devices being configured for operation in lock-step; and
assigning device IDs for each DRAM device, corresponding DRAM devices on different channels having the same device ID, the device IDs being arranged in a manner to reduce heat flux associated with the one or more memory modules.

### Claim 35 (depends on 34)

The method of claim 34, wherein the memory module comprises two or more DRAM devices on each channel.

### Claim 36 (depends on 34)

The method of claim 34, wherein the memory module comprises four or more DRAM devices on each channel.

### Claim 37 (depends on 34)

The method of claim 34, wherein the memory module comprises four or more DRAM devices on each face.

### Claim 38 (depends on 34)

The method of claim 34, wherein the memory module comprises eight or more DRAM devices on the module.

### Claim 39 (depends on 34)

The method of claim 34, wherein the memory module comprises DRAM devices on each face.

### Claim 40 (depends on 34)

The method of claim 34, wherein said assigning is performed by a memory controller that is operably connected to the memory module.

### Claim 41

A memory module comprising:
front and back faces;
one or more device on each face;
a control line connecting devices on each of the faces in a manner to reduce heat flux associated with the memory module.

### Claim 42 (depends on 41)

The memory module of claim 41, wherein all of the devices are corresponding devices that commonly contribute multiple bits to a data bus.

### Claim 43 (depends on 41)

The memory module of claim 41, wherein the control line alternates between devices on each of the faces.

### Claim 44 (depends on 41)

The memory module of claim 41, wherein the control line connects multiple devices on both the front and back face.

### Claim 45 (depends on 44)

The memory module of claim 44, wherein at least some of the connected devices on a face are disposed adjacent one another.

### Claim 46 (depends on 41)

The memory module of claim 41, comprising four or more devices on a face.

### Claim 47 (depends on 41)

The memory module of claim 41, comprising at least eight devices per module.

### Claim 48 (depends on 41)

The memory module of claim 41, wherein the devices comprise DRAMs.

### Claim 49

A method comprising:
providing a memory module comprising front and back faces, and multiple devices on each face; and
connecting devices on each of the faces by routing a control line through the memory module in a manner to reduce heat flux associated with the memory module.

### Claim 50 (depends on 49)

The method of claim 49, wherein the control line alternates between devices on each of the faces.

### Claim 51 (depends on 49)

The method of claim 49, wherein the control line connects multiple devices on both the front and back face.

### Claim 52 (depends on 51)

The method of claim 51, wherein at least some of the connected devices on a face are disposed adjacent one another.

### Claim 53 (depends on 49)

The method of claim 49, comprising four or more devices on a face.

### Claim 54 (depends on 49)

The method of claim 49, comprising at least eight devices per module.

### Claim 55 (depends on 49)

The method of claim 49, wherein the devices comprise DRAM devices.