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US 6,721,223 B2Granted
Semiconductor memory device
AssigneeRenesas Technology Corp.
InventorsJunko Matsumoto, Tadaaki Yamauchi, Takeo Okamoto
Life of this patent
Estimating the term…
Abstract
Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a control signal and a refresh address that are required for refresh. Stored data can be stably held in the self-refresh mode in which data holding is performed with reduced current consumption.
Claims19
A semiconductor memory device comprising:
- a memory array having a plurality of memory cells;
- refresh circuitry for refreshing storage data of a memory cell in said memory array;
- a register circuit for storing data setting at least one of a refresh period and a refresh region of said memory array, said register circuit storing externally applied refresh specifying data in response to an externally applied register set instruction signal;
- and
- refresh execution control circuitry for generating, in refresh execution, a refresh address specifying a memory cell to be refreshed in said memory array, and supplying said refresh address to and activating said refresh circuitry, according to data stored in said register circuit, wherein
- said refresh specifying data comprises region specifying data specifying a refresh target region of said memory array to be refreshed, and
- said refresh execution control circuitry includes:
- a counter for generating a counter address in a refresh operation mode of performing the refresh;
- and
- a circuit for modifying the counter address in accordance with the region specifying data to change the counter address into an address in said refresh target region to generate said refresh address.
7 more elements
A semiconductor memory device comprising:
- a plurality of banks, each having a plurality of memory cells arranged in rows and columns, driven to a selected state independently of each other;
- refresh address generation circuitry for generating a refresh address for refreshing memory cells of said plurality of banks in a refresh operation, said refresh address generation circuitry including a circuit for generating a refresh bank address specifying a bank of said plurality of banks, said refresh bank address specifying a part of said plurality of banks in a low power consumption mode, and specifying all the banks in a mode different from said low power consumption mode;
- and
- refresh execution control circuitry for executing refresh on a memory cell of a bank specified by the refresh address from said refresh address generation circuitry.
1 more element
Dependencies are inferred from the claim text.