Sense amplifier and architecture for open digit arrays

A memory circuit, comprising:

• a plurality of sense amplifiers fabricated over a substrate each of said sense amplifiers comprising:
• a pair of p-channel transistors and a pair of n-channel transistors, said pair of n-channel transistors being associated with a first active area;
• a first interconnect line connecting one of said p-channel transistors with one of said n-channel transistors;
• a second interconnect line connecting the other of said p-channel transistor with the other of said n-channel transistor;
• an equalization circuit comprising of at least two n-channel transistors being associated with said first active area;
• and
• a pair of digit lines coupled to each of said sense amplifiers respectively connected between said pair of p-channel transistors and said pair of n-channel transistors at said first and second interconnect lines such that said pair of p-channel transistors are on a first side of said pair of digit lines, and said pair of n-channel transistors and said equalization circuit are on a second side of said pair of digit lines.

A processor system, comprising:

• a processor;
• and
• memory device coupled to said processor, said memory device comprising:
• at least one sense amplifier fabricated over a substrate comprising:
• first and second n-channel transistors;
• first and second p-channel transistors;
• a first interconnect line connecting said first n-channel and said first p-channel transistors;
• a second interconnect line connecting said second n-channel and said second p-channel transistors;
• an equalization circuit;
• and
• a pair of digit lines coupled to said at least one sense amplifier by said first and second interconnect lines such that said first and second n-channel transistors and said equalization circuit are on a first side of said pair of digit lines, and said first and second p-channel transistors are on a second side of said pair of digit lines.

An integrated memory circuit, comprising:

• a die containing a processor and a memory device, said memory device comprising:
• at least one sense amplifier fabricated over a substrate comprising:
• first and second n-channel transistors
• first and second p-channel transistors;
• a first interconnect line connecting said first n-channel and said first p-channel transistors;
• a second interconnect line connecting said second n-channel and said second p-channel transistors;
• an equalization circuit;
• and
• a pair of digit lines coupled to said at least one sense amplifier by said first and second interconnect lines such that said first and second n-channel transistors and said equalization circuit are on a first side of said pair of digit lines, and said first and second p-channel transistors are on a second side of said pair of digits lines.

A memory circuit, comprising:

• a plurality of sense amplifiers fabricated over a substrate each of said sense amplifiers comprising:
• two p-channel transistors and two n-channel transistors;
• a first interconnect line connecting a gate of one of said p-channel transistors with a gate of one of said n-channel transistors, said first interconnect line being substantially linear;
• a second interconnect line connecting a gate of the other of said p-channel transistors with a gate of the other of said n-channel transistors, said second interconnect line being substantially linear;
• and
• a pair of digit lines coupled to each of said sense amplifiers such that said two p-channel transistors are on a first side of said pair of digit lines, and said two n-channel transistors are on a second side of said pair of digit lines, and said pair of digit lines are coupled orthogonally to respective interconnect lines.