# US 6,721,220 B2 · Bit line control and sense amplification for TCCT-based memory cells

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- Number: US 6,721,220 B2
- Document ID: US6721220B2
- Status: Granted
- Kind: B2
- Application number: 10/191,686
- Filed: 2002-07-05
- Published: 2004-01-08
- Granted: 2004-04-13
- Earliest claimed: 2002-07-05
- Assignees: T-Ram, Inc.
- Inventors: Sei-Seung Yoon; Seong-Ook Jung
- Web page: https://patentgrep.com/patent/US6721220B2

## CPC

- G11C 11/39: using thyristors {or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

## Claims

### Claim 1

A sensing circuit including a sense amplifier to resolve a data signal generated by a TCCT-based memory cell, the sensing circuit comprising:
a bit line coupled to the TCCT-based memory cell to receive the data signal;
a first pre-charge device coupled to the bit line and configured to pre-charge the bit line;
a reference bit line configured to receive a reference signal from a reference memory cell; and
a second pre-charge device coupled to the reference bit line and configured to pre-charge the reference bit line.

### Claim 2 (depends on 1)

The sensing circuit of claim 1, further comprising a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line.

### Claim 3 (depends on 2)

The sensing circuit of claim 2, further comprising a first switchable device to temporally couple the first node to the bit line.

### Claim 4 (depends on 3)

The sensing circuit of claim 3, wherein the first switchable device is a MOSFET device.

### Claim 5 (depends on 1)

The sensing circuit of claim 1, wherein the first pre-charge device includes a second switchable device to couple the bit line to a pre-charge node, where the pre-charge node is at least one pre-determined level.

### Claim 6 (depends on 5)

The sensing circuit of claim 5, wherein the at least one pre-determined level is a potential equivalent to ground.

### Claim 7 (depends on 5)

The sensing circuit of claim 5, wherein the second switchable device is a MOSFET device.

### Claim 8 (depends on 1)

The sensing circuit of claim 1, wherein the sense amplifier comprises two cross-coupled inverters.

### Claim 9 (depends on 8)

The sensing circuit of claim 8, further comprising a sensing power switchable device coupled between the sense amplifier and another potential to enable operation of the sense amplifier.

### Claim 10 (depends on 1)

The sensing circuit of claim 1, further comprising:
a second node connected to a second input of the sense amplifier, the second node configured to couple with the reference bit line.

### Claim 11 (depends on 1)

The sensing circuit of claim 1, wherein the reference memory cell includes a TCCT device cell.

### Claim 12 (depends on 10)

The sensing circuit of claim 10, further comprising a third switchable device to temporally couple the second node to the reference bit line.

### Claim 13 (depends on 12)

The sensing circuit of claim 12, wherein the third switchable device is a MOSFET device.

### Claim 14 (depends on 1)

The sensing circuit of claim 1, wherein the second pre-charge device includes a fourth switchable device to couple the reference bit line to a reference pre-charge node, where the reference pre-charge node is at least one pre-determined reference level.

### Claim 15 (depends on 14)

The sensing circuit of claim 14, wherein the at least one pre-determined reference level is equivalent to the at least one pre-determined level.

### Claim 16 (depends on 14)

The sensing circuit of claim 14, wherein the fourth switchable device is a MOSFET device.

### Claim 17 (depends on 10)

The sensing circuit of claim 10, further comprising a fifth and a sixth switchable device configured to communicate complementary signals from the first and the second nodes, respectively.

### Claim 18

A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell, the sensing circuit comprising:
a bit line coupled to the memory cell to receive the data signal;
a first node connected to a first input of the sense amplifier, the first node configured to couple with the bit line;
a first pre-charge device coupled to the bit line to pre-charge the bit line to a first pre-determined level; and
a second pre-charge device coupled to the first node to pre-charge the bit line to a second pre-determined level.

### Claim 19 (depends on 18)

The sensing circuit of claim 18, wherein the memory cell is a TCCT-based memory cell.

### Claim 20 (depends on 18)

The sensing circuit of claim 18, further comprising a first MOSFET device to couple the first node to the bit line.

### Claim 21 (depends on 18)

The sensing circuit of claim 18, wherein the first pre-charge device includes a second MOSFET device to couple the bit line to a first pre-charge node, where the first pre-charge node is at the first pre-determined level.

### Claim 22 (depends on 21)

The sensing circuit of claim 21, wherein the first pre-determined level is a potential equivalent to ground.

### Claim 23 (depends on 18)

The sensing circuit of claim 18, wherein the second pre-charge device includes a third MOSFET device to couple the first node to a second pre-charge node, where the second pre-charge node is at the second pre-determined level.

### Claim 24 (depends on 23)

The sensing circuit of claim 23, wherein the second pre-determined level is a potential equivalent to ground.

### Claim 25 (depends on 18)

The sensing circuit of claim 18, wherein the sense amplifier comprises two cross-coupled inverters.

### Claim 26 (depends on 25)

The sensing circuit of claim 25, further comprising a sensing power MOSFET device coupled between the sense amplifier and another potential to enable operation of the sense amplifier.

### Claim 27 (depends on 18)

The sensing circuit of claim 18, wherein the sense amplifier is configured to receive a reference signal generated by a reference memory cell, the sensing circuit further comprising:
a reference bit line coupled to the reference memory cell to receive the data signal;
a second node connected to a second input of the sense amplifier, the second node configured to couple with the reference bit line;
a third pre-charge device coupled to the reference bit line to pre-charge the reference bit line to a third pre-determined level; and
a fourth pre-charge device coupled to the second node to pre-charge the bit line to a fourth pre-determined level.

### Claim 28 (depends on 27)

The sensing circuit of claim 27, wherein the reference memory cell includes a TCCT device.

### Claim 29 (depends on 27)

The sensing circuit of claim 27, further comprising a fourth MOSFET device to couple the second node to the reference bit line.

### Claim 30 (depends on 27)

The sensing circuit of claim 27, wherein the third pre-charge device includes a fifth MOSFET device to couple the reference bit line to a third pre-charge node, where the third pre-charge node is at the third pre-determined level.

### Claim 31 (depends on 30)

The sensing circuit of claim 30, wherein the third pre-determined level is a potential equivalent to ground.

### Claim 32 (depends on 27)

The sensing circuit of claim 27, wherein the fourth pre-charge device includes a sixth MOSFET device to couple the second node to a fourth pre-charge node, where the fourth pre-charge node is at the fourth pre-determined level.

### Claim 33 (depends on 32)

The sensing circuit of claim 32, wherein the fourth pre-determined level is a potential equivalent to ground.

### Claim 34 (depends on 27)

The sensing circuit of claim 27, wherein the sense amplifier comprises two cross-coupled inverters.

### Claim 35

A method of controlling a sensing circuit, the method comprising:
coupling a bit line to a first node, the first node associated with a first sense amplifier input;
pre-charging the bit line to a first pre-determined level;
pre-charging the first node to the first pre-determined level;
floating the bit line;
floating the first node; and
transferring a data signal from a TCCT-based memory cell onto the bit line.

### Claim 36 (depends on 35)

The method of claim 35, further comprising resolving the data signal including:
applying the data signal from the bit line to the first node;
decoupling the bit line and the first node; and
determining a logical value in which the data signal represents.

### Claim 37 (depends on 35)

The method of claim 35, further comprising enabling operation of a sense amplifier.

### Claim 38 (depends on 35)

The method of claim 35, wherein the coupling of the bit line to the first node is during non-resolving operation of the sense amplifier.

### Claim 39 (depends on 35)

The method of claim 35, the method further comprising:
coupling a reference bit line to a second node, the second node associated with a second sense amplifier input;
pre-charging the reference bit line to a second pre-determined level;
pre-charging the second node to the second pre-determined level;
floating the reference bit line;
floating the second node; and
transferring a reference signal from a reference memory cell onto the reference bit line.

### Claim 40 (depends on 39)

The method of claim 39, wherein the coupling the reference bit line to the second node is during non-resolving operation of the sense amplifier.

### Claim 41 (depends on 39)

The method of claim 39, wherein the reference memory cell includes a TCCT device.

### Claim 42 (depends on 39)

The method of claim 39, further comprising using the reference signal including:
applying the reference signal from the reference bit line to the second node; and
decoupling the reference bit line and the second node.

### Claim 43

A method of controlling a sensing circuit, the method comprising:
floating a bit line;
pre-charging a first node to a first pre-determined level;
pre-charging the bit line to a second pre-determined level;
coupling the bit line to the first node, the first node associated with a first sense amplifier input; and
floating the first node.

### Claim 44

A method of controlling a sensing circuit, the method comprising:
floating a bit line;
pre-charging a first node to a first pre-determined level;
pre-charging the bit line to a second pre-determined level;
coupling the bit line to the first node, the first node associated with a first sense amplifier input; and
transferring a data signal from a thinly capacitively-coupled thyristor based memory cell onto the bit line.

### Claim 45 (depends on 44)

The method of claim 44, further comprising resolving the data signal including:
applying the data signal from the bit line to the first node;
decoupling the bit line and the first node; and
determining a logical value in which the data signal represents.

### Claim 46 (depends on 45)

The method of claim 45, further comprising enabling operation of a sense amplifier.

### Claim 47

A method of controlling a sensing circuit, the method comprising:
floating a bit line;
pre-charging a first node to a first pre-determined level;
pre-charging the bit line to a second pre-determined level; and
coupling the bit line to the first node, the first node associated with a first sense amplifier input;
wherein the coupling of the bit line to the first node is approximately near or prior in time to the application of the data signal from the bit line to the first node.

### Claim 48

A method of controlling a sensing circuit, the method comprising:
floating a bit line;
pre-charging a first node to a first pre-determined level;
pre-charging the bit line to a second pre-determined level;
coupling the bit line to the first node, the first node associated with a first sense amplifier input;
floating a reference bit line;
pre-charging a second node to a third pre-determined level;
pre-charging the bit line to a fourth pre-determined level; and
coupling the reference bit line to the second node, the second node associated with a second sense amplifier input.

### Claim 49 (depends on 48)

The method of claim 48, further comprising floating the second node.

### Claim 50 (depends on 49)

The method of claim 49, further comprising transferring a reference signal from a memory cell onto the bit line.

### Claim 51 (depends on 48)

The method of claim 48, wherein the reference memory cell includes a TCCT device.

### Claim 52 (depends on 50)

The method of claim 50, further comprising:
applying the reference signal from the reference bit line to the second node; and
decoupling the reference bit line and the second node.

### Claim 53 (depends on 48)

The method of claim 48, wherein the first, the second, the third and the fourth pre-determined levels are equivalent to ground.