Method and circuit arrangement for reading out and for storing binary memory cell signals

Method for reading out binary memory cell signals from a memory cell array and for storing binary memory cell signals in a memory cell array, having the following steps:

• a) application of at least one binary memory cell signal from a plurality of memory cells to a plurality of bit line pairs, wherein the bit line pairs are arranged to run rectilinearly and to have minimal bevels;
• b) switching-through of the binary memory cell signals from the memory cells via the bit line pairs a plurality of sense amplifiers by means of at least one memory cell array switching transistor pair in a manner dependent on at least one memory cell array control signal fed via at least one memory cell array control;
• c) switching-through of a binary output signals of the sense amplifiers to a local data line pair as a binary intermediate signal by means of at least one local data line switching transistor pair in a manner dependent on a column control signal fed via a column control line;
• d) switching-through of the binary intermediate signal of the local data line pair to at least one main data line pair by means of at least one main data line switching transistor pair in a manner dependent on a row control signal fed via a row control line;
• and
• e) outputing of a binary output signal via the main data line pair.