# US 6,721,216 B2 · Memory addressing structural test

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- Number: US 6,721,216 B2
- Document ID: US6721216B2
- Status: Granted
- Kind: B2
- Application number: 09/823,597
- Filed: 2001-03-30
- Published: 2002-10-03
- Granted: 2004-04-13
- Earliest claimed: 2001-03-30
- Assignees: Intel Corporation
- Inventors: Tak M. Mak; Michael R. Spica; Michael J. Tripp
- Web page: https://patentgrep.com/patent/US6721216B2

## CPC

- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus and method for testing an address decoder and word lines of a memory array comprised of connecting a signature analyzer to the word lines emanating from an address decoder, setting a clock used to trigger the latching of the states of the word lines by the signature analyzer, transmitting an address to the address decoder to be decoded, and triggering the signature analyzer to latch the state of the word lines.

## Claims

### Claim 1

An apparatus, comprising:
an address decoder;
a plurality of word lines emanating from the address decoder;
at least one memory cell connected to at least one of the word lines; and
a signature analyzer connected to at least two of the plurality of word lines.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the address decoder decodes a portion of a memory address.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the at least one memory cell is a dynamic RAM memory cell.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the at least one memory cell is a static RAM memory cell.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the address decoder and the signature analyzer are connected to opposite ends of at least one of the plurality of word lines.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the signature analyzer latches the state of at least one of the plurality of word lines in response to a clock.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the timing of the clock is adjustable.

### Claim 8

A method, comprising:
setting the timing of a clock used to trigger the latching of inputs to a signature analyzer;
transmitting an address to an address decoder connected to the inputs of the signature analyzer through a plurality of word lines;
decoding the address using the address decoder; and
triggering the signature analyzer with the clock to latch the state of the plurality of word lines connected to the inputs of the signature analyzer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising examining the output of the signature analyzer for each address decoded to determine if the correct word line was turned on, and to determine if any other word line was turned on for that address.

### Claim 10 (depends on 8)

The method of claim 8, further comprising examining the output of the signature analyzer for a plurality of addresses decoded to determine if the correct word line was turned on, and to determine if any other word line was turned on for all of the plurality of addresses.

### Claim 11 (depends on 8)

The method of claim 8, further comprising setting the timing of the clock to a plurality of different settings to determine which ones of the plurality of word lines operate more slowly.

### Claim 12 (depends on 8)

The method of claim 8, further comprising setting the timing of the clock so that the plurality of word lines are tested at a desired operating speed.

### Claim 13

An apparatus, comprising:
an address decoder;
a signature analyzer;
a plurality of circuits organized into a two-dimensional array comprising a first circuit, a second circuit, a third circuit and a fourth circuit;
a first word line coupled to the address decoder, the signature analyzer, the first circuit and the second circuit; and
a second word line coupled to the address decoder, the signature analyzer, the third circuit and the fourth circuit.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the address decoder decodes at least a portion of a memory address.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the first, second, third and fourth circuits are memory cells.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the first, second, third and fourth circuits are programmable logic devices.

### Claim 17 (depends on 13)

The apparatus of claim 13, wherein the address decoder and the signature analyzer are connected to opposite ends of the first and second word lines.

### Claim 18 (depends on 13)

The apparatus of claim 13, wherein the signature analyzer latches the state of at least one of the plurality of word lines in response to a clock.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the timing of the clock is adjustable.