Voltage boosting circuit for a low power semiconductor memory

A voltage boosting circuit that operates entirely from a single, common VCC voltage supply for boosting the output voltage of a wordline driver for a DRAM circuit, comprising:

• an NMOS pass transistor having a gate input terminal, a drain terminal, and a source output terminal at which is provided a boosted output voltage vh for a wordline of a DRAM;
• a gate preboost capacitor having a first terminal connected to a gate preboost terminal and having a second terminal;
• a gate preboost precharge circuit connected to the gate preboost terminal for precharging the first terminal of the gate preboost capacitor from the common VCC voltage supply, wherein said gate preboost precharge circuit has a PMOS precharge transistor that has its source terminal connected to the common VCC voltage supply and that has a drain terminal and a substrate terminal connected together in common to the first terminal of the gate preboost capacitor and to the gate preboost terminal;
• means for connecting the second terminal of the gate preboost capacitor to a common ground while the gate preboost precharge circuit precharges the first terminal of the preboost capacitor from the common VCC voltage supply to provide a precharged gate preboost capacitor;
• means for connecting the second terminal of the precharged gate preboost boost capacitor to the common VCC voltage to thereby boost the precharged gate preboost terminal voltage to 2 VCC;
• a gate boost capacitor having a first terminal connected to the gate input terminal of the NMOS pass transistor and having a second terminal;
• a gate precharge circuit connected to the gate input terminal of the NMOS pass transistor for precharging the first terminal of the gate boost capacitor from the common VCC voltage supply, wherein said gate precharge circuit has a PMOS gate precharge transistor that has its source terminal connected to the gate preboost terminal and that has a drain terminal and a substrate terminal connected together in common to the first terminal of the gate boost capacitor;
• means for connecting the second terminal of the gate boost capacitor to a common ground while the gate precharge circuit precharges the first terminal of the gate boost capacitor from the common VCC voltage supply to provide a precharged gate boost capacitor;
• means for connecting the second terminal of the precharged gate boost capacitor to the precharge terminal that has been precharged to 2 VCC to thereby boost the precharged gate input terminal voltage to 3 VCC;
• a drain boost capacitor having a first terminal connected to the drain input terminal of the NMOS pass transistor and having a second terminal;
• a drain precharge circuit connected to the drain terminal of the NMOS pass transistor for precharging the drain terminal of the NMOS pass transistor with the common VCC voltage supply, wherein said drain precharge circuit has a PMOS drain precharge transistor that has its source terminal connected to the common VCC voltage supply and that has its drain terminal and a substrate terminal connected together in common to the drain terminal of the NMOS pass transistor to precharge the drain terminal of the NMOS pass transistor;
• means for connecting the second terminal of the drain boost capacitor to a common ground, while the drain precharge circuit precharges the first terminal of the drain boost capacitor from the common VCC voltage supply to provide a precharge drain boost capacitor;
• means for connecting the second terminal of the drain boost capacitor to the common VCC voltage level to thereby boost the precharged drain terminal voltage to 2 VCC and to provide a boosted output voltage for a wordline of a DRAM at a level of 2 VCC minus the threshold voltage for the NMOS pass transistor.