Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJae Woon Kim
Life of this patent
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Abstract
A semiconductor memory device suitable for rapidly transferring output data from sense amplifiers to an output-buffer is disclosed. The semiconductor memory device includes a plurality of sense amplifiers respectively connected to a plurality of cell blocks. A first common output-line is connected to a first set of sense amplifiers associated with a first set of cell blocks. A second common output-line is connected to a second set of sense amplifiers associated with a second set of cell blocks. A loading selection circuit selects one of the first and second common output-lines so as to transfer output data from a selected sense amplifier, via the selected one of the first and second common output-lines, to another device, such as an output-buffer.
Claims14
A semiconductor memory comprising:
- a plurality of upper cell blocks;
- a plurality of upper sense amplifiers respectively connected to the plurality of upper cell blocks, each of the upper sense amplifiers having a separate output-line;
- a first common output-line connected to the separate output-line of each of the upper sense amplifiers;
- a plurality of lower cell blocks;
- a plurality of lower sense amplifiers respectively connected to the plurality of upper cell blocks, each of the lower sense amplifiers having a separate output-line;
- a second common output-line connected to the separate output-line of each of the lower sense amplifiers;
- and
- a loading selection circuit connected to the first and second common output-lines and for selecting one of the first and second common output-lines in response to a block selection address signal.
A semiconductor memory device comprising:
- a plurality of upper cell blocks;
- a plurality of upper sense amplifiers respectively connected to the plurality of upper cell blocks, each of the upper sense amplifiers having a separate output-line;
- a first common output-line connected to separate output-line of each of the upper sense amplifiers;
- a plurality of lower cell blocks;
- a plurality of lower sense amplifiers respectively connected to the plurality of upper cell blocks, each of the lower sense amplifiers having a separate output-line;
- a second common output-line connected to the separate output-line of each of lower sense amplifiers;
- a loading selection circuit connected to the first and second common output-lines and for selecting one of the first and second common output-lines in response to a block selection address signal and
- an output-buffer connected to the loading selection circuit for buffering an output value of the loading selection circuit.
Dependencies are inferred from the claim text.