Nonvolatile ferroelectric memory device and method for operating main bitline load controller thereof

A nonvolatile ferroelectric memory device comprising:

• a plurality of cell array blocks provided with a plurality of sub cell array blocks having a plurality of unit cells;
• a plurality of main bitlines arranged in the sub cell array blocks in one direction for each unit of column;
• a plurality of sub bitlines connected with the unit cells to induce a voltage in the unit cells of the sub cell array blocks and arranged along the main bitlines;
• a plurality of main bitline load controllers arranged at least in lower and upper areas of the sub cell array blocks so that one end of each of the main bitline load controllers is connected with the main bitlines and the other end of said each of the main bitline load controllers is connected with a high level applying terminal;
• a sensing amplifier block including a plurality of sensing amplifiers commonly used in the cell array blocks and amplifying signals of the main bitlines;
• and
• switching control blocks including first, second, and third switching transistors controlling whether to connect the sub bitlines and the main bitlines with the sub cell array blocks and controlling pull-up and pull-down of the sub bitlines;
• a fourth switching transistor controlled by the sub bitlines having the voltage value induced from the unit cells and sensing the voltage of the main bitlines by varying a current value depending on data values of the unit cells;
• a column selector block including a plurality of column selectors corresponding to the sub cell array blocks;
• a reference generator block including a plurality of reference generators corresponding to the sensing amplifiers;
• and
• a main bitline pull-up block pulling up the main bitlines.

A method for operating a main bitline load controller of a nonvolatile ferroelectric memory device, the method comprising:

• preparing the nonvolatile ferroelectric memory device which includes a plurality of sub cell array blocks having a plurality of unit cells, and a plurality of cell array blocks provided with main bitline load controllers driven by a main bitline load control signal at the uppermost and lowest areas of the sub cell array blocks;
• selecting a cell driving area;
• and
• turning on at least one main bitline load controller nearest to the sub cell array block corresponding to the selected cell driving area.