Nonvolatile ferroelectric memory device and driving method thereof
AssigneeHynix Corporation
InventorHee Bok Kang
Life of this patent
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Abstract
A nonvolatile ferroelectric memory device includes a plurality of sense amplifiers, top and bottom cell array units disposed respectively at an upper and a lower sections, the top and bottom cell array units each including a plurality of unit cells, and being disposed symmetrically about the sense amplifiers. The nonvolatile ferroelectric memory device further includes at least one top reference array unit, at least one bottom reference array unit, a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit, and a plurality of reference bit lines of the bottom or top cell array unit. Reference bit lines of the top or bottom cell array unit correspond to main bit lines of the bottom or top cell array unit disposed symmetrically about the sense amplifiers.
Claims29
A nonvolatile ferroelectric memory device comprising:
- a plurality of sense amplifiers;
- a top cell array unit disposed at an upper section, and a bottom cell array unit disposed at a lower section, the top and bottom cell array units each including a plurality of unit cells, and the top and bottom cell array units being disposed symmetrically about the sense amplifiers;
- at least one top reference array unit in a vicinity of the top cell array unit, and at least one bottom reference array unit in a vicinity of the bottom cell array unit;
- a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit;
- and
- a plurality of reference bit lines of the bottom or top cell array unit, wherein reference bit lines of the bottom cell array unit correspond to main bit lines of the top cell array unit disposed symmetrically about the sense amplifiers, and reference bit lines of the top cell array unit correspond to main bit lines of the bottom cell array unit disposed symmetrically about the sense amplifiers.
A nonvolatile ferroelectric memory device comprising:
- a top cell array unit including a plurality of unit cells;
- a bottom cell array unit including a plurality of unit cells;
- a middle reference array unit disposed in a middle area between the top and bottom cell array units;
- a plurality of edge reference array units disposed at edge sections of the top and bottom cell array units, respectively;
- and
- a plurality of sense amplifiers,
- wherein the top cell array unit is disposed at an upper section, the bottom cell array unit is disposed at a lower section, the top and bottom cell array units being disposed symmetrically about the sense amplifiers,
- wherein the sense amplifiers are disposed alternately to lie each between the top and bottom cell array units, or between the top cell array unit and an edge reference array unit, or between the bottom cell array unit and an edge reference array unit,
- wherein bit lines at the lower section below the sense amplifiers disposed between the top and bottom cell array units and the edge reference array units are main bit lines when the bit lines at the upper section above the sense amplifiers disposed between the top and bottom cell array units and the edge reference array units are reference bit lines, and
- wherein the bit lines at the lower section below the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the reference bit lines when the bit lines at the upper section above the sense amplifiers formed between the top and bottom cell array units and the edge reference array units are the main bit lines.
A nonvolatile ferroelectric memory device comprising:
- top and bottom cell array units disposed at an upper and a lower sections symmetrical about a plurality of sense amplifiers, each cell array unit including a plurality of unit cells;
- a plurality of reference array units disposed at edge sections of the top and bottom cell array units corresponding to the sense amplifiers, respectively;
- a plurality of bit lines wherein two of the bit lines of the top cell array unit and two of the corresponding bit lines of the bottom cell array unit share one of the sense amplifiers, wherein the bit lines at the lower area symmetrical about the sense amplifiers are used as reference bit lines when the bit lines at the upper area symmetrical about the sense amplifiers are used as main bit lines, and wherein two bit lines adjacent to the main and reference bit lines at the upper and lower sections are used as dummy reference bit lines;
- and
- a plurality of switching devices receiving first and second control signals to control whether to connect the sense amplifiers and bit lines to each other, wherein corresponding bit lines from the upper and lower sections are symmetrical about the sense amplifiers and are controlled by the same control signal.
In a nonvolatile ferroelectric memory device including top and bottom cell array units disposed at upper and lower sections symmetrical about sense amplifiers to include a plurality of unit cells, respectively, at least one reference array unit disposed in a vicinity of each of the top and bottom cell array units to correspond to each other, and bit lines disposed on the upper and lower sections to share the sense amplifiers, respectively, a method of driving the nonvolatile ferroelectric memory device having the feature that a reference voltage generated from the reference array unit is applied to the bit lines disposed at the lower sections below the sense amplifiers so that the bit lines at the lower sections operate as reference bit lines when the bit lines disposed at the upper sections above the sense amplifiers operate as main bit lines.
Dependencies are inferred from the claim text.