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US 6,721,197 B1Granted
Antifuse memory cell and antifuse memory cell array
AssigneeActel Corporation
InventorJohn McCollum
Life of this patent
Estimating the term…
Abstract
An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode of the first antifuse is connected to the first electrode of the second antifuse, and the drain of the MOS transistor is connected to said first electrode of the first antifuse and the first electrode of the second antifuse.
Claims2
A method of programming an antifuse memory cell comprising:
- providing an antifuse memory cell comprising:
- a first antifuse having a first electrode coupled to a control gate of a first pass transistor coupling a first portion of a logic path to a second portion of a logic path through an output node and a second electrode coupled to a pull-up voltage source;
- a second antifuse having a first electrode coupled to said control gate of said first pass transistor through said output node and a second electrode coupled to a pull-down voltage source;
- and
- a second pass transistor having a drain coupled to said first electrode of said first antifuse and said first electrode of said second antifuse, a source coupled to a memory data output line, and a control gate coupled to a Y SELECT signal line;
- applying Vpp to second electrode of said first antifuse;
- applying Vpp/2 to said second electrode of said second antifuse;
- and
- applying an active Y SELECT signal to said Y SELECT signal line of said control gate of said second pass transistor and selectively placing said drain of said second pass transistor connected to said first electrode of said first antifuse and said first electrode of said second antifuse at ground and programming said first antifuse.
6 more elements
A method of programming an antifuse memory cell comprising:
- providing an antifuse memory cell comprising:
- a first antifuse having a first electrode coupled to a control gate of a first pass transistor coupling a first portion of a logic path to a second portion of a logic path through an output node and a second electrode coupled to a pull-up voltage source;
- a second antifuse having a first electrode coupled to said control gate of said first pass transistor through said output node and a second electrode coupled to a pull-down voltage source;
- and
- a second pass transistor having a drain coupled to said output node, a source coupled to a memory data output line and a control gate coupled to a Y SELECT signal line;
- applying Vpp to said second electrode of said second antifuse;
- applying Vpp/2 to said second electrode of said first antifuse;
- and
- applying an active Y select signal to said Y SELECT signal line of said control gate of said second pass transistor and selectively placing said drain of said second pass transistor connected to said first electrode of said first antifuse and said first electrode of said second antifuse at ground and programming said second antifuse.
6 more elements
Dependencies are inferred from the claim text.