# US 6,721,196 B1 · Semiconductor memory chip module

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- Number: US 6,721,196 B1
- Document ID: US6721196B1
- Status: Granted
- Kind: B1
- Application number: 09/926,791
- Filed: 2002-03-22
- Granted: 2004-04-13
- Earliest claimed: 1999-06-23
- Assignees: Giesecke & Devrient GmbH
- Inventors: Thomas Grassl
- Web page: https://patentgrep.com/patent/US6721196B1

## CPC

- H10W 90/00: Package configurations
- G06K 19/073: Special arrangements for circuits, e.g. for protecting identification code in memory (protection against unauthorised use of computer memory G06F12/14)
- G06K 19/077: Constructional details, e.g. mounting of circuits in the carrier
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS

## Abstract

In a semiconductor memory chip module (2′) for a smart card, a nonvolatile memory chip (EEPROM) (4) and a volatile memory chip (SRAM) (6) are stacked and coupled directly by vertical chip interconnections (16). The rapid-access volatile memory permits fast execution of programs. Permanent and safe storage of data is effected by reloading the data to the nonvolatile memory. A chip (8) with decoder circuits can be contained in a further level. Likewise integrated into a chip is a buffer capacitor (20) which is constantly recharged to a constant supply voltage during operation.

## Claims

### Claim 1

A semiconductor memory chip module comprising:
a first memory chip of a first type;
a second memory chip a second type; and
an electric connection between the first and second memory chips;
wherein the memory chips are disposed one above the other in different levels and connected by vertical chip interconnections;
wherein memory cells of the first memory chip are firmly allocated to certain memory cells of the second memory chip, and the mutually allocated memory cells are directly interconnected electrically.

### Claim 2 (depends on 1)

A chip module according to claim 1, wherein the first type corresponds to a nonvolatile memory, for example EEPROM, and the second type to a volatile memory, for example SRAM.

### Claim 3 (depends on 1)

A chip module according to claim 1, wherein at least one further chip is provided in a further level.

### Claim 4 (depends on 3)

A chip module according to claim 3, wherein the further chip contains decoder circuits for the memory chips.

### Claim 5 (depends on 1)

A chip module according to claim 1, wherein an energy buffer is formed in at least one of the levels.

### Claim 6 (depends on 5)

A chip module according to claim 5, wherein the energy buffer is formed as an integrated buffer capacitor.

### Claim 7 (depends on 1)

A chip module according to claim 1, formed for a smart card.

### Claim 8 (depends on 1)

A smart card having a semiconductor memory chip module according to claim 1.