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US 6,721,194 B2Granted
Semiconductor memory
AssigneeRenesas Technology Corp.
InventorsTomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Abstract
A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.
Claims20
A semiconductor memory comprising:
- a plurality of memory cells wherein each of said plurality of memory cells is connected at one of a plurality of intersections between a plurality of word lines and a plurality of bit lines;
- a one-bit flag memory cell included for each word line;
- a plurality of sense amplifiers associated with said plurality of bit lines;
- a plurality of data registers randomly accessible and holding writable data items;
- including a number of 1s and a number 0s;
- an encoding control circuit for making a determination of a ratio of the number of 1s to the number of 0s among the writable data items;
- and
- encoders for writing the writable data items in said sense amplifiers as they are or by inverting the data items according to the ratio determined by said encoding control circuit.
5 more elements
Dependencies are inferred from the claim text.