Cache memory
AssigneeSTMicroelectronics S.r.l.
InventorWilliam Bryan Barnes
Life of this patent
Estimating the term…
Abstract
A cache memory and method for operating a cache memory are provided which comprise a tag RAM, tag RAM sense amplifier circuitry, data RAM sense amplifier circuitry and decision circuitry. Timing difficulties exist in determining whether or not a hit has occurred and in outputting the data from the data RAM upon occurrence of a hit. Upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and is compared with input address information. A decision is reached as to whether or not identity exists. Only when the result of that decision has been validly determined can data be output.
Claims50
A cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry for selectively enabling said data RAM sense amplifier circuitry, said decision circuitry having a first input for stored tag data and a second input for address data, said decision circuitry having a first valid state when said tag data matches said address data and a second valid state different to said first valid state when said tag data differs from said address data, said decision circuitry having a control input for setting said decision circuitry to an invalid state different to said valid states, wherein said decision circuitry has first and second nodes, said nodes being at complementary logic levels in said valid output states and at a common potential in said invalid state.
A method of operating a cache memory having a stored tag data, an input for address data, a data RAM, data RAM sense amplifier circuitry and decision circuitry for selectively enabling said data RAM sense amplifier circuitry, said decision circuitry having a first and a second node, the method comprising:
- sensing stored tag data;
- comparing said stored tag data with input address data;
- and
- setting said first and second nodes to a common potential, wherein said comparing step comprises:
- providing a first logic level on the first node and a second opposite logic level on the second node in response to a match between said stored tag data and said input address data;
- and
- providing said second logic level on the first node and said second opposite logic level on the first node when said stored tag data differs from said address data.
A cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry for providing a read enable signal to a read enable terminal of said data RAM sense amplifier circuitry, said decision circuitry having a first input for stored tag data, a second input for address data and a pair of intermediate nodes, a first of said intermediate nodes being at logic 1 and the second being at logic 0 when said tag data matches said address data, the second of said intermediate nodes being at logic 1 and the first being at logic 0 when said tag data differs from said address data, said decision circuitry having a control input for setting said nodes to a common potential, wherein said decision circuitry further comprises logic circuitry being responsive to said first and second intermediate nodes and operable to provide a read enable signal to said read enable terminal only in response to said match, wherein said logic circuitry has a control input and said logic circuitry responds to a predetermined logic state at said control input to provide said read enable signal to said read enable terminal whenever said intermediate nodes have complementary levels.
A method of operating a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry laving a read enable input, the method comprising:
- sensing stored tag data;
- comparing said sensed tag data with input address data;
- establishing a first circuit condition and maintaining said first circuit condition until a valid comparison is achieved and upon achieving a valid comparison:
- establishing a second circuit condition when a match is detected between said sensed tag data and said input address data;
- establishing a third circuit condition when no match is detected, in response to said step of establishing said second condition:
- generating a read enable signal;
- and
- supplying said read enable signal to said read enable input, the method further comprising:
- determining an input at a control terminal to selectively provide said read enable signal to said read enable terminal responsive to said step of establishing said third condition.
A cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry, the tag RAM sense amplifier circuitry having an enable input for receiving a sense amplifier enable signal, the decision circuitry having a first input for stored tag data, a second input for address data and a control input for enabling said decision circuitry, the data RAM sense amplifier circuitry having a disable input terminal and a read input terminal, said decision circuitry providing a data read signal to said read input terminal of said data RAM sense amplifier circuitry when a match exists between said stored tag data and said address data, the memory further comprising:
- timing circuitry responsive to said sense amplifier enable signal for maintaining a first level at said control input thereby holding an output of said decision circuitry in an inactive condition for a given period, and thereafter applying a second level at said control input, thereby allowing said output to become active;
- and
- logic circuitry sensing an active output of said decision circuitry for supplying a disabling signal to said disable input terminal, thereby disabling said data RAM sense amplifier circuitry until after said output of said decision circuitry becomes active.
A method of operating a cache memory having a tag RAM, tag RAM sense amplifier circuitry, a data RAM, data RAM sense amplifier circuitry and decision circuitry, the tag RAM sense amplifier circuitry having an enable input for receiving a sense amplifier enable signal, the decision circuitry having a first input for stored tag data, a second input for address data and a control input for enabling said decision circuitry, the data RAM sense amplifier circuitry having a disable input terminal and a read input terminal, the method comprising:
- providing a disabling signal to said disable input terminal, thereby disabling said data RAM sense amplifier circuitry;
- maintaining a first level at said control input thereby holding an output of said decision circuitry in an inactive condition for a given period after said sense amplifier enable signal;
- thereafter applying a second level at said control input, thereby allowing said output to become active;
- sensing the output of said decision circuitry;
- in response to an active output, terminating supply of said disabling signal to said disable input terminal;
- and
- providing a data read signal to said read input terminal of said data RAM sense amplifier circuitry when a match exists between said stored tag data and said address data.
Dependencies are inferred from the claim text.