# US 6,721,150 B1 · Clamping circuit for use in computer system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,721,150 B1 - Document ID: US6721150B1 - Status: Granted - Kind: B1 - Application number: 09/736,846 - Filed: 2000-12-12 - Granted: 2004-04-13 - Earliest claimed: 2000-12-12 - Assignees: Advanced Micro Devices, Inc. - Inventors: Edward C. Guerrero, Jr.; Barry Kent Kates; Christopher Eric Tressler - Web page: https://patentgrep.com/patent/US6721150B1 ## CPC - H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract A clamping circuit and method for use in a computer system are provided. In the computer system, a voltage regulator supplies a voltage rail to various components in the system. This voltage rail may be susceptible to voltage spikes or other over-voltage conditions, such as when the voltage rail provides the input voltage to a switching regulator. The clamping circuit comprises a detecting stage and a clamping stage. The detecting stage detects when the voltage rail increases beyond a first voltage level. If this increase is detected, the detecting stage activates the clamping stage, which begins reducing the voltage rail. Once the voltage rail decreases beneath the first voltage level, the detecting stage stops activating the clamping stage. In this way, the clamping circuit protects the computer system from voltage spikes on the voltage rail. ## Claims ### Claim 1 A computer system, comprising: system memory; a voltage regulator configured to provide a supply voltage to a plurality of components in the computer system, wherein one of the components is a switching regulator; the switching regulator, wherein the switching regulator is configured to regulate the supply voltage and to provide a termination voltage, separate from the supply voltage, to the system memory; and a clamping circuit, wherein the clamping circuit comprises a detecting stage and a clamping stage, wherein the detecting stage is configured to activate the clamping stage when the supply voltage exceeds a first voltage level, and wherein the clamping stage is coupled to the detecting stage and configured to reduce the supply voltage in response to being activated by the detecting stage. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the system memory comprises DDR SDRAM. ### Claim 3 (depends on 1) The computer system of claim 1, wherein the detecting stage comprises a voltage divider coupled to the supply voltage and configured to monitor the supply voltage, wherein the voltage divider provides a voltage activating the clamping stage when the supply voltage exceeds the first voltage level. ### Claim 4 (depends on 1) The computer system of claim 1, wherein the clamping stage is configured to reduce the supply voltage by shunting current to ground. ### Claim 5 (depends on 4) The computer system of claim 4, wherein the clamping stage comprises a shunt regulator. ### Claim 6 (depends on 5) The computer system of claim 5, wherein the clamping stage further comprises a transistor, wherein the shunt regulator is configured to provide a base current to the transistor, and wherein the transistor is configured to reduce the supply voltage by shunting current to ground when provided with the base current. ### Claim 7 (depends on 1) The computer system of claim 1, wherein the first voltage level is lower than a maximum voltage level. ### Claim 8 (depends on 7) The computer system of claim 7, wherein the clamping stage is further configured to prevent the supply voltage from exceeding the maximum voltage level. ### Claim 9 (depends on 7) The computer system of claim 7, wherein the maximum voltage level is a voltage level that causes erroneous behavior in a first portion of the components provided with the supply voltage. ### Claim 10 (depends on 1) The computer system of claim 1, wherein the detecting stage is further configured to not activate the clamping stage when the supply voltage does not exceed the first voltage level. ### Claim 11 (depends on 1) The computer system of claim 1, wherein the clamping stage is further configured to stop reducing the supply voltage when the detecting stage stops detecting that the supply voltage exceeds the first voltage level. ### Claim 12 A method of operating a computer system, comprising: providing a voltage rail to a plurality of components in the computer system, wherein the voltage rail is provided by a linear regulator, and wherein the plurality of components comprise a switching regulator; providing a termination voltage, separate from the supply voltage, to system memory, wherein the termination voltage is provided by the switching regulator; detecting when the voltage rail exceeds a first voltage level; and clamping the voltage rail in response to said detecting so that the voltage rail does not exceed a maximum voltage level, wherein the maximum voltage level is a voltage level that causes erroneous behavior in a first portion of the components provided with the voltage rail. ### Claim 13 (depends on 12) The method of claim 12, wherein the system memory comprises DDR SDRAM. ### Claim 14 (depends on 12) The method of claim 12, wherein said clamping only occurs while the voltage rail is detected to be exceeding the first voltage level. ### Claim 15 (depends on 12) The method of claim 12, wherein said detecting comprises using a voltage divider to measure the voltage rail. ### Claim 16 (depends on 12) The method of claim 12, wherein said clamping comprises shunting current from the voltage rail to ground. ### Claim 17 (depends on 12) The method of claim 12, wherein said clamping comprises activating a shunt regulator, wherein the shunt regulator is configured to shunt current to ground when activated. ### Claim 18 (depends on 12) The method of claim 12, wherein said clamping comprises using a shunt regulator to activate a transistor coupled to the voltage rail, wherein the transistor is configured to shunt current from the voltage rail to ground when activated. ### Claim 19 (depends on 12) The method of claim 12, wherein said clamping is done quickly enough that the voltage rail does not exceed the maximum voltage level. ### Claim 20 (depends on 19) The method of claim 19, wherein the first voltage level is lower than the maximum voltage level. ### Claim 21 A clamping circuit configured to clamp a voltage rail in a computer system, comprising: a voltage divider coupled to the voltage rail and to a shunt regulator, wherein the voltage divider is configured to apply an input voltage to the shunt regulator, wherein the voltage divider is configured so that the input voltage is greater than or equal to a reference voltage level of the shunt regulator when a voltage on the voltage rail is greater than or equal to a first voltage level, and wherein the voltage divider is configured so that the input voltage is less than the reference voltage level when the voltage on the voltage rail is less than the first voltage level; the shunt regulator coupled to the voltage divider, wherein the shunt regulator is configured to turn on when the input voltage is greater than or equal to the reference voltage level and turn off when the input voltage is less than the reference voltage level; and a transistor coupled to the voltage rail and to the shunt regulator, wherein the transistor is configured to turn on in response to the shunt regulator turning on, wherein the transistor is configured to sink current from the voltage rail when the transistor is on to decrease the voltage on the voltage rail below first voltage level while the voltage rail is being supplied by a power supply, and wherein the transistor is further configured to turn off when the shunt regulator is off. ### Claim 22 (depends on 21) The clamping circuit of claim 21, further comprising a current-limiting resistor coupled between the shunt regulator and the transistor.