Precompensation circuit for magnetic recording

A method of precompensating magnetic recording of data signals comprising the steps of:

• generating clock signals at a predetermined rate in successive clock periods to clock the data signals to be recorded;
• generating clock delay data relative to the generated clock signal for each successive data signal to be recorded responsive to a pattern of adjacent data signals;
• and
• sequentially controlling recording times of the successive data signals by n>1 clock delay units, each clock delay unit generating an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the clock delay unit for the one data signal of the sequence.

A precompensation circuit for magnetic recording of data signals comprising:

• clock means for generating clock signals at a predetermined rate in successive clock periods to clock the data signals to be recorded;
• clock delay generating means for generating clock delay data relative to the generated clock signal for each successive data signal to be recorded responsive to a pattern of adjacent data signals;
• and
• n>1 clock delay means for controlling recording times of the successive data signals, each clock delay means operating to generate an output signal for determining the recording time of one data signal in each sequence of n successive data signals responsive to the clock delay data received by the clock delay means in the sequence for the one data signal.

In a precompensation circuit for magnetic recording of data signals having a clock generating clock signals at a predetermined rate in successive clock periods to clock the data signals to be recorded, a computer usable medium having computer readable program units embodied therein comprising:

• a first program unit for determining clock delay data for each successive data signal responsive to a pattern of adjacent data signals;
• and
• a second program unit for controlling sequential operation of n>1 programmable clock delay units to determine the recording time of the successive data signals,
• wherein each programmable clock delay unit is controlled to generate an output signal for determining the recording time of one of the data signals in each sequence of n successive data signals responsive to the clock delay data received by the clock data unit for the one data signal in the sequence.