Dirty tag bits for 3D-RAM SRAM

A graphics system comprising:

• a memory array configured to receive and store graphics data, wherein the memory array comprises:
• a plurality of DRAM banks, wherein each DRAM bank is logically subdivided into pages, and wherein each page is further subdivided into blocks,
• a plurality of level two write-through caches connected to the DRAM banks, wherein the number of level two caches is equal to the number of DRAM banks, and wherein the storage capacity of each of the level two caches is equal to a page,
• a level one write-back cache connected to the level two caches and configured to receive and store a plurality of graphics data blocks;
• an array of memory circuits configured to store the status of the graphics data stored in the level one cache, wherein the status indicates whether the graphics data is modified or unmodified;
• and
• a cache controller connected to the level two caches, the level one cache, and the array of memory circuits, wherein the cache controller is configured to control the transfer of graphics data between the caches according to the contents of the memory circuits;
• a request preprocessor configured to receive requests for graphics data accesses to the memory array, wherein the request preprocessor transforms the requests into memory commands according to stored tags indicating contents of the level-one cache and the level-two caches, and wherein the memory commands comprise cache commands and pixel commands;
• a cache queue connected to the request preprocessor and to the cache controller, wherein the cache queue stores the cache commands and delivers the cache commands to the cache controller on a first-in-first-out basis, wherein the cache controller asserts memory control signals to direct page fetches from the DRAM banks to the level two caches and block fetches from the level two caches to the level one cache in response to the cache commands;
• a pixel queue connected to the request preprocessor, wherein the pixel queue stores the pixel commands and outputs the pixel commands on a first-in-first-out basis;
• and
• a pixel request processor connected to the pixel queue, wherein the pixel request processor controls the transfer of graphics data into and out of the level one cache according to the pixel commands.

A method for accessing pixel data in a memory array, wherein the method comprises:

• a) arithmetically combining pixel data with the contents of a temporary storage space of the memory array, wherein the result is stored in the temporary storage space;
• b) maintaining an array of status bits, external to the memory array, indicative of whether or not data stored in the temporary storage space has been modified;
• c) periodically determining if any of the status bits indicate that the corresponding data within a block of the temporary storage space has been modified;
• d) issuing a request to write the block of data to a level two cache of the memory array if the corresponding status bits indicate that the data has been modified;
• e) copying only the modified data in the block, as indicated by the corresponding status bits, from the temporary storage space to the level two cache;
• f) changing the state of the status bits corresponding to the block of data to indicate the associated data is unmodified;
• g) receiving requests for graphics data accesses to the memory array and generating memory commands in response to the access requests according to stored tags indicating contents of the temporary storage space and the level two cache, wherein the memory commands comprise cache commands and pixel commands;
• h) storing the cache commands in a first queue and storing the pixel commands in a second queue, wherein the first queue and second queue are configured as first-in-first-out buffers;
• i) reading cache commands from the first queue and asserting control signals to direct page fetches from a DRAM bank of the memory array to the level two cache and block fetches from the level two cache to the temporary storage space in response to the cache commands;
• and
• j) reading pixel commands from the second queue and asserting control signals to direct transfers of graphics data into and out of the temporary storage space according to the pixel commands.

A method for externally managing cached pixel data within a 3D-RAM memory device, the method comprising:

• identifying a block within a level one cache of the 3D-RAM, wherein the block is either a target or a source for a data block transfer with a level two cache of the 3D-RAM;
• maintaining status bits, external to the 3D-RAM, for each data block in the level one cache;
• setting one or more of the status bits to a known state in response to a data block transfer, wherein the known state indicates that the data within the associated block of level one cache is unmodified;
• and
• identifying write operations to the level one cache, wherein the source of the write data is external to the 3D-RAM;
• setting a status bit associated with a data value, in the level one cache, targeted by a write operation, to a known state in response to the write operation, wherein the known state indicates the data value within the level one cache has been modified;
• synchronizing the data in the level two cache to the data in the level one cache according to the state information stored in the status bits;
• receiving requests for graphics data accesses to the 3D-RAM and generating memory commands in response to the access requests according to stored tags indicating contents of the level one cache and the level two cache, wherein the memory commands comprise cache commands and pixel commands;
• storing the cache commands in a first queue and storing the pixel commands in a second queue, wherein the first queue and second queue are configured as first-in-first-out buffers;
• reading cache commands from the first queue and asserting control signals to direct page fetches from a DRAM bank of the 3D-RAM to the level two cache and block fetches from the level two cache to the level one cache in response to the cache commands;
• and
• reading pixel commands from the second queue and asserting control signals to direct transfers of graphics data into and out of the level one cache according to the pixel commands.

A method for reducing the power consumption in a 3D-RAM, the method comprising:

• associating dirty tag bits with pixels stored in a level one cache of the 3D-RAM, wherein the dirty tag bits are external to the 3D-RAM, wherein the state of a dirty tag bit indicates that the associated pixel is dirty if the pixel has been modified or clean if the pixel has not been modified;
• grouping the dirty tag bits into status words, wherein a status word is associated with one and only one block of the level one cache memory;
• writing-back blocks of pixel data within the level one cache to a level two cache of the 3D-RAM according to the contents of the status words, wherein only dirty pixels are written-back;
• receiving requests for graphics data accesses to the 3D-RAM and generating memory commands in response to the access requests according to stored tags indicating contents of the level one cache and the level two cache, wherein the memory commands comprise cache commands and pixel commands;
• storing the cache commands in a first queue and storing the pixel commands in a second queue, wherein the first queue and second queue are configured as first-in-first-out buffers;
• reading cache commands from the first queue and asserting control signals to direct page fetches from a DRAM bank of the 3D-RAM to the level two cache and block fetches from the level two cache to the level one cache in response to the cache commands;
• and
• reading pixel commands from the second queue and asserting control signals to direct transfers of graphics data into and out of the level one cache according to the pixel commands.