Interpolation circuit having a conversion error connection range for higher-order bits and A/D conversion circuit utilizing the same

An interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising:

• a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a first voltage dividing element array (NT1) disposed between the non-inverted output terminals of the first and the second differential amplifiers;
• a second voltage dividing element array (NT2) disposed between the inverted output terminals of the first and the second differential amplifiers;
• a fifth voltage dividing element array (NT5) disposed between the non-inverted output terminal of the first differential amplifier and the inverted output terminal of the second differential amplifier;
• and
• a sixth voltage dividing element array (NT6) disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier;
• wherein the interpolation differential voltages are generated from nodes in the first voltage dividing element array and from nodes in the second voltage dividing element array, and the extrapolation differential voltages are generated from between nodes in the fifth voltage dividing element array and in the sixth voltage dividing element array.

An interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising:

• a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a seventh voltage dividing element array (NT7) disposed between the non-inverted output terminals of the first and the second differential amplifiers;
• an eighth voltage dividing element array (NT8) disposed between the inverted output terminals of the first and the second differential amplifiers;
• a ninth voltage dividing element array (NT9) disposed between a first node in the seventh voltage dividing element array and a second node in the eighth voltage dividing element array;
• and
• a tenth voltage dividing element array (NT10) disposed between a second node in the seventh voltage dividing element array and a first node in the eighth voltage dividing element array;
• wherein the interpolation differential voltages are generated from nodes in the seventh voltage dividing element array and from nodes in the eighth voltage dividing element array, and the extrapolation differential voltages are generated from nodes in the seventh or eighth voltage dividing element array and from nodes in the ninth or tenth voltage dividing element array.

An interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising:

• a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a seventh voltage dividing element array (NT7) disposed between the non-inverted output terminals of the first and the second differential amplifiers;
• an eighth voltage dividing element array (NT8) disposed between the inverted output terminals of the first and the second differential amplifiers;
• a ninth voltage dividing element array (NT9) disposed between a first node in the seventh voltage dividing element array and a second node in the eighth voltage dividing element array;
• a tenth voltage dividing element array (NT10) disposed between a second node in the seventh voltage dividing element array and a first node in the eighth voltage dividing element array;
• and
• a third voltage dividing element array (NT3) disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier;
• wherein the interpolation differential voltages are generated from nodes in the seventh voltage dividing element array and from nodes in the eighth voltage dividing element array, and the extrapolation differential voltages are generated from nodes in the third voltage dividing element array.

An interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprising:

• a first differential amplifier for inputting the first differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a second differential amplifier for inputting the second differential input voltage and generating a differential output voltage between an inverted output terminal and a non-inverted terminal thereof;
• a seventh voltage dividing element array (NT7) disposed between the non-inverted output terminals of the first and the second differential amplifiers;
• an eighth voltage dividing element array (NT8) disposed between the inverted output terminals of the first and the second differential amplifiers;
• a ninth voltage dividing element array (NT9) disposed between a first node in the seventh voltage dividing element array and a second node in the eighth voltage dividing element array;
• a tenth voltage dividing element array (NT10) disposed between a second node in the seventh voltage dividing element array and a first node in the eighth voltage dividing element array;
• a fifth voltage dividing element array (NT5) disposed between the non-inverted output terminal of the first differential amplifier and the inverted output terminal of the second differential amplifier;
• and
• a sixth voltage dividing element array (NT6) disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier;
• wherein the interpolation differential voltages are generated from nodes in the seventh voltage dividing element array and from nodes in the eighth voltage dividing element array, and the extrapolation differential voltages are generated from between nodes in the fifth voltage dividing element array and in the sixth voltage dividing element array.