US 6,720,830 B2Granted

Low-power, differential optical receiver in silicon on insulator

AssigneeThe Johns Hopkins University

InventorsAndreas G. Andreou, Alyssa Apsel

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Abstract

A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage (22) followed by a plurality of differential feed-forward, high-bandwidth gain stages (24) and a final, differential-to-single-ended converter output stage (26). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk. The circuit design is well-suited for use in a multi-dimensional array of optical interconnects between CMOS chips or platforms.

Claims17

Dependent claims

A complimentary metal oxide semiconductor (CMOS) differential amplifier, comprising:

a first transistor including a first node coupled to a voltage source, and a second node and a gate node coupled to each other, such that said first transistor is configured as a self-biased current source;
a second transistor including a first node coupled to the voltage source, and a second node and a gate node coupled to each other, such that said second transistor is configured as a self-biased current source;
a third transistor including a first node coupled to the second node of said first transistor and serving as a first output node, a second node, and a gate node serving as a first input node and configured to receive a first input signal;
a fourth transistor including a first node coupled to the second node of said second transistor and serving as a second output node, a second node coupled to the second node of said third transistor, and a gate node serving as a second input node and configured to receive a second input signal;
and
a fifth transistor including a first node coupled to the second nodes of said third and fourth transistors, a second node coupled to ground, and a gate node configured to receive a bias signal such that said fifth transistor operates as a current source;
wherein gate threshold voltages of said third and fourth transistors are greater than gate threshold voltages of said first, second and fifth transistors.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/166,052Filed 11 Jun 2002 · us provisional application
Priority: 11 Jun 2001
Published: US 2003/0025562 A16 Feb 2003
Granted: 13 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/082
Controlled by light: with FET's
H03F 3/45475
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using IC blocks as the active…
H03F 2203/45601
Indexing scheme relating to differential amplifiers: the IC comprising one or more passive resistors by feedback