Dual edge-triggered flip-flop design with asynchronous programmable reset
AssigneeSun Microsystems, Inc.
InventorsGin S. Yee, Pradeep R. Trivedi, Joseph R. Siegel
Life of this patent
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Abstract
A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.
Claims19
A dual edge-triggered flip-flop programmably resetable independent of an input clock signal, comprising:
- control circuitry arranged to receive the input clock signal and a reset signal;
- negative edge-triggered circuitry operatively connected to the control circuitry and arranged to receive a data signal and a reset value signal, wherein the negative edge-triggered circuitry generates a first output value dependent on the control circuitry and the data signal;
- positive edge-triggered circuitry operatively connected to the control circuitry and arranged to receive the data signal and the reset value signal, wherein the positive edge-triggered circuitry generates a second output value dependent on the control circuitry and the data signal;
- and
- output circuitry operatively connected to the negative edge-triggered circuitry and the positive edge-triggered circuitry, wherein the output circuitry generates an output signal dependent on one selected from a group consisting of the first output value and the second output value,
- wherein, upon assertion of the reset signal, the output signal is set to a value of the reset value signal asynchronous of the input clock signal.
A dual edge-triggered flip-flop programmably resetable asynchronous of an input clock signal, comprising:
- control means for receiving the input clock signal and a reset signal;
- negative edge-triggered means for generating a first output value dependent on the control means and a data signal;
- positive edge-triggered means for generating a second output value dependent on the control means and the data signal;
- and
- output means for generating an output signal dependent on one selected from a group consisting of the first output value and the second output value,
- wherein, upon assertion of the reset signal, the output signal is set to a programmed value asynchronous of the input clock signal.
A method for performing a dual edge-triggered flip-flop operation, comprising:
- inputting a data signal, a reset signal, and a reset value signal;
- latching a first value on a positive edge of an input clock signal dependent on the data signal;
- latching a second value on a negative edge of the input clock signal dependent on the data signal;
- generating an output signal dependent on the input clock signal, an enable signal, and one selected from a group consisting of the first value and the second value;
- and
- upon assertion of the reset signal, setting the output signal to a value of the reset value signal asynchronous of the input clock signal.
Dependencies are inferred from the claim text.