# US 6,720,812 B2 · Multi-channel integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,720,812 B2 - Document ID: US6720812B2 - Status: Granted - Kind: B2 - Application number: 10/279,004 - Filed: 2002-10-24 - Published: 2003-07-31 - Granted: 2004-04-13 - Earliest claimed: 1997-06-27 - Assignees: Nova R&D, Inc. - Inventors: Tumay O Tumer; Gerard Visser - Web page: https://patentgrep.com/patent/US6720812B2 ## CPC - H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof - H04N 25/707: Pixels for event detection - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/773: comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities. ## Claims ### Claim 1 A data readout integrated circuit having a plurality of integrated circuit channels comprising a plurality of inputs coupled to a plurality of detectors, wherein the plurality of inputs are coupled to plurality of input amplifiers, for providing a plurality of readout signals amplified from a plurality of detector signals, wherein each input amplifier is part of a readout channel wherein each readout channel comprises: a means for receiving a detector signal; a charge sensitive amplifier coupled to said means for receiving a detector signal, for integrating said detector signal and producing a signal output; at least one shaper amplifier responsive to said charge sensitive amplifier signal output; a processing circuit connected to the shaper amplifier for processing a charge sensitive amplifier output to generate readout signals, and a means for outputting said readout signals responsive to said detector signals. ### Claim 2 (depends on 1) The data readout integrated circuit of claim 1, wherein a polarity switching circuit is included. ### Claim 3 (depends on 2) The data readout integrated circuit of claim 2, wherein said polarity switching circuit is externally controlled. ### Claim 4 (depends on 1) The data readout integrated circuit of claim 1, further comprising a gain stage coupled to said charge sensitive amplifier. ### Claim 5 (depends on 1) The data readout integrated circuit of claim 1, wherein said shaped, integrated detector signal is of an approximately inverted bell shaped form. ### Claim 6 (depends on 1) The data readout integrated circuit of claim 1, wherein said shaped, integrated detector signal is of an approximate uninverted bell shaped form. ### Claim 7 (depends on 1) The data readout integrated circuit of claim 1, further comprising a peak hold circuit coupled to output of shaper amplifier, wherein peak hold circuit have output which is coupled to a first plurality of comparators. ### Claim 8 (depends on 7) The data readout integrated circuit of claim 7, wherein a first comparator of said plurality of comparators is a low level discriminator, and wherein at least one of said first comparator allows an output trigger when a peak hold circuit output is larger than a first threshold voltage. ### Claim 9 (depends on 8) The data readout integrated circuit of claim 8, further comprising a second comparator of said plurality of comparators wherein said second comparator is an upper level discriminator, and wherein said second comparator only issues a signal when said peak hold circuit output is larger than a second threshold voltage. ### Claim 10 (depends on 9) The data readout integrated circuit of claim 9, wherein said first comparator and said second plurality of comparator enclose at least one predetermined energy band. ### Claim 11 (depends on 9) The data readout integrated circuit of claim 9, further comprising a differentiator circuit coupled to at least one of said first plurality of comparators, said differentiator circuit producing a fast trigger output with low jitter. ### Claim 12 (depends on 7) The data readout integrated circuit of claim 7, wherein an output of said peak hold circuit is multiplexed to said means for outputting. ### Claim 13 (depends on 9) The data readout integrated circuit of claim 9, wherein an output of at least one of said comparator or said second plurality of comparator initiates a readout cycle of said data readout integrated circuit. ### Claim 14 (depends on 1) The data readout integrated circuit of claim 1, wherein said means for outputting outputs a trigger signal for a channel of said plurality of integrated circuit channels containing a detected signal. ### Claim 15 (depends on 14) The data readout integrated circuit of claim 14, wherein said data outputting means only outputs said readout signal for said channel of said plurality of integrated circuit channels for which a trigger signal has been received. ### Claim 16 (depends on 14) The data readout integrated circuit of claim 14, wherein said data outputting means outputs said readout signal for said channel of said plurality of integrated circuit channels after said trigger signal has been received for any one of said plurality of integrated circuit channels. ### Claim 17 (depends on 16) The data readout integrated circuit of claim 16, wherein said trigger signal is an external trigger signal. ### Claim 18 (depends on 1) The data readout integrated circuit of claim 1, wherein a data outputting means outputs a readout signal for one triggered channel of said plurality of integrated circuit channels an disables all remaining channels of said plurality of integrated circuit channels, wherein a time delay between said readout signal and said disablement of said remaining channels is controlled by an externally supplied signal. ### Claim 19 (depends on 1) The data readout integrated circuit of claim 1, wherein said input charge sensitive amplifier has a resistive feedback in parallel to a capacitance feedback.