Dual-edge-correcting clock synchronization circuit
AssigneeXilinx, Inc.
InventorBernard J. New
Life of this patent
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Abstract
A clock distribution circuit and method in which the incoming clock frequency is divided by two to create a reduced-frequency global clock signal. A dual-edge-correcting clock synchronization circuit aligns both the rising and falling edges of the global clock signal to separately to nullify the clock-distribution errors associated with rising and falling clock edges.
Claims14
A dual-edge-correcting clock synchronization circuit comprising:
- a. a clock divider circuit receiving a clock signal;
- b. a rising-edge correcting synchronization circuit having a first synchronization-circuit input terminal connected to the clock divider circuit and a first synchronization-circuit output terminal providing a rising-edge corrected clock signal;
- c. a falling-edge correcting synchronization circuit having a second synchronization-circuit input terminal connected to the clock divider circuit and a second synchronization-circuit output terminal providing a falling-edge corrected clock signal;
- and
- d. a clock-combining circuit having first and second clock-combining-circuit input terminals and a clock-combining-circuit output terminal, wherein the first and second clock-combining-circuit input terminals are connected to the respective first and second synchronization-circuit output terminals.
A method of synchronizing a reference clock signal with a feedback-clock signal, the feedback-clock signal including a sequence of rising and falling edges, the method comprising:
- a. comparing a first series of edges of the reference clock signal with the rising edges of the feedback-clock signal to produce a first error-correction factor wherein the reference clock signal comprises a frequency divider clock signal;
- and
- b. comparing a second series of edges of the reference clock signal with the falling edges of the feedback-clock signal to produce a second error-correction factor.
A dual-edge-correcting clock synchronization circuit comprising:
- a. a clock terminal adapted to provide a clock signal, the clock terminal connected to a clock divider circuit;
- b. a feedback-clock terminal receiving a feedback-clock signal;
- c. a first single-edge-correcting synchronization circuit having:
- i. a first synchronization-circuit input terminal connected to the clock terminal;
- ii. a second synchronization-circuit input terminal connected to the feedback-clock terminal;
- and
- iii. a first control port;
- iv. wherein the first single-edge-correcting synchronization circuit provides, on the first control port, a first control signal derived from a first synchronization error between a rising edge on the first synchronization-circuit input terminal and a rising edge on the second synchronization-circuit input terminal;
- and
- d. a second single-edge-correcting synchronization circuit having:
- i. a third synchronization-circuit input terminal connected to the clock terminal;
- ii. a fourth synchronization-circuit input terminal connected to the feedback-clock terminal;
- and
- iii. a second control port;
- iv. wherein the second single-edge-correcting synchronization circuit provides, on the second control port, a second control signal derived from a second synchronization error between a falling edge on the third synchronization circuit input terminal and a falling edge on the fourth synchronization circuit input terminal.
Dependencies are inferred from the claim text.