Method and system for a CMOS power up circuit with adjustable threshold

A system for a power up circuit for producing a power up signal for an integrated circuit device, comprising:

• a plurality of long channel transistor chains, wherein each of the long channel transistor chains are configured to provide a respective resistance value;
• first and second select lines coupled to the long channel transistor chains and configured to enable a selected one of the long channel transistor chains;
• a VCC input coupled to the long channel transistor chains;
• and
• an output latch for generating a power up signal, the output latch coupled to the long channel transistor chains and to the VCC input, the output latch configured to keep the power up signal deasserted until a voltage from the selected one long channel transistor chain rises past a switch on threshold as VCC rises, whereupon the output latch asserts the power up signal and maintains the power up signal asserted in the presence of noise on the VCC input, and wherein each of the plurality of long channel transistor chains is configured to provide a respective switch on threshold by providing a respective resistance when enabled by the first and second select lines.

A method for producing a power up signal for an integrated circuit device using a CMOS power up circuit, comprising:

• generating a plurality of different resistance values by using a plurality of transistor chains;
• enabling a selected one of the transistor chains by using first and second select lines coupled to the transistor chains;
• and
• generating a reliable power up signal by using an output latch coupled to the transistor chains and to a VCC input, the output latch configured to keep the power up signal deasserted until a voltage from the selected one transistor chain rises past a switch on threshold as VCC rises, whereupon the output latch asserts the power up signal and maintains the power up signal asserted in the presence of noise on the VCC input.