Semiconductor device with clock generation circuit
AssigneeRenesas Technology Corp.
InventorsTakashi Kubo, Hisashi Iwamoto
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Abstract
An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.
Claims4
A semiconductor device operating in synchronization with an external clock signal, comprising:
- a clock generation circuit generating an internal clock signal in synchronization with said external clock signal;
- an output circuit providing a data signal output from said semiconductor device in response to said internal clock signal;
- and
- an impedance adjustment circuit generating an impedance adjustment signal to adjust an output impedance of said output circuit,
- said clock generation circuit including a replica delay circuit to delay said internal clock signal for a predetermined time corresponding to a predetermined time of a data signal output operation of said output circuit,
- said impedance adjustment circuit applying said impedance adjustment signal to said output circuit and also to said replica delay circuit.
Dependencies are inferred from the claim text.