Class AB digital to analog converter/line driver

A differential line driver comprising:

• first, second, third and fourth cascode transistors driven by a first voltage, wherein drains of the first and third transistors are connected to a first output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a second output of the differential line driver;
• first, second, third and fourth switching transistors connected in series with corresponding first, second, third and fourth cascode transistor and each driven by a corresponding data signal;
• and
• first and second compound transistors inputting a class AB operation signal to control output currents of the compound transistors,
• wherein the first compound transistor is connected to sources of the first and second switching transistors,
• wherein the second compound transistor is connected to sources of the third and fourth switching transistors, and
• wherein an effective channel length of the first and second compound transistors is variable.

A differential line driver comprising:

• first, second, third and fourth cascode transistors driven by a first voltage, wherein drains of the first and third transistors are connected to a first output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a second output of the differential line driver;
• first, second, third and fourth switching transistors connected in series with corresponding first, second, third and fourth cascode transistors and each driven by a corresponding data signal;
• and
• first and second compound transistors inputting a class AB operation signal to control output currents of the compound transistors,
• wherein the first compound transistor is connected to sources of the first and second switching transistors,
• wherein the second compound transistor is connected to sources of the third and fourth switching transistors, and
• wherein an effective channel width of the first and second compound transistors is variable.

A differential line driver comprising:

• first, second, third and fourth cascode transistors driven by a first voltage, wherein drains of the first and third transistors are connected to a first output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a second output of the differential line driver;
• first, second, third and fourth switching transistors connected in series with corresponding first, second, third and fourth cascode transistors and each driven by a corresponding data signal;
• and
• first and second compound transistors inputting a class AB operation signal to control output currents of the compound transistors,
• wherein the first compound transistor is connected to sources of the first and second switching transistors,
• wherein the second compound transistor is connected to sources of the third and fourth switching transistors, and
• wherein total charge injected at a bias terminal of the first compound transistor is substantially zero.

A differential line diver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cells including:
• first and second cascode transistors;
• first and second switching transistors connected in series with the first and second cascode transistors an each driven by a corresponding data signal;
• and
• a compound transistor inputting a class AB operation signal to change its output current and connected to sources of the first and second switching transistors,
• wherein the compound transistor includes first, second and third FET's connected in series with each other and with sources of the first and second switching transistors, and a fourth FET connected across the second FET, a gate of the fourth FET driven by the class AB signal.

A differential line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including:
• first and second cascode transistors;
• first and second switching transistors connected in series with the first and second switching transistors, and each driven by a corresponding date signal;
• and
• a tail current transistor driven by a bias voltage and connected to sources of the first and second switching transistors,
• wherein total change injected at a gate of the tail current transistor is substantially zero during switching.

A differential line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including:
• first and second, cascode transistors
• first and second switching transistors connected in series with the first and second cascode transistors and each driven by a corresponding data signal;
• and
• a compound transistor inputting a class AB operation signal to change its output current and connected to sources of the first and second switching transistors,
• wherein an effective channel length of the compound transistor is variable.

A differential line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including:
• first and second cascode transistors;
• first and second switching transistors connected in series with the first and second cascode transistors and each driven by a corresponding data signal;
• and
• a compound transistor and inputting a class AB operation signal to change its output current and connected to sources of the first and second switching transistors,
• wherein an effective channel width of the compound transistor is variable.

A class AB line driver comprising:

• first and second half-cells cross connected to positive and negative differential outputs, each half-cell including:
• first and second cascode transistors;
• first and second switching transistors connected in series with the first and second cascode transistors respectively;
• and
• a tail current transistor inputting a bias voltage at its gate and connected to sources of the first and second switching transistors,
• wherein the bias voltage spikes lasts less than a clock cycle of the data inputted to the class AB line during switching for Gigabit Ethernet operation and 100TX mode.

A programmable line driver comprising:

• a plurality of cells, each cell's output current selectively controlled by a class AB operation signal and each cell including first and second half-cells cross connected to outputs of opposite polarity, each half-cell including:
• first and second cascode transistors;
• first and second switching transistors each connected in series with the first and second cascode transistors respectively;
• and
• a compound transistor inputting a bias signal at its gate and connected to sources of the first and second switching transistors, the compound transistor switched to class AB operation by the class AB operation signal,
• wherein same polarity outputs of the cells are added.

A line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative outputs, each half-cell including:
• first and second cascode transistors connected in parallel;
• first and second switching transistors connected in series with the respective first and second cascode transistors;
• and
• a variable effective channel length transistor inputting a signal that changes its effective channel length at its gate and connected between sources of the first and second switching transistors and ground.

A line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative outputs, each half-cell including:
• first and second cascode transistors connected in parallel;
• first and second switching transistors connected in series with the respective first and second cascode transistors;
• and
• a variable aspect ratio transistor inputting a signal that changes its effective channel length at its gate and connected between sources of the first and second switching transistors and ground.

A differential line driver comprising:

• first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including:
• first and second switching transistors each driven by a corresponding data signal;
• and
• a compound transistor inputting a class AB operation signal to change its output current and connected to sources of the first and second switching transistors,
• wherein one of effective channel width and effective channel length of the compound transistor changes based on the class AB operation signal.

A differential line driver comprising:

• a plurality of switching transistors connected to corresponding polarity outputs of the differential line driver;
• and
• a plurality of tail current transistors with variable aspect ratios inputting a class AB operation signal at their gates to control their output current and connected in series with corresponding switching transistors,
• wherein the tail current transistor is switched to class AB operation by the class AB operation signal.

A line driver comprising:

• first and second half-cells cross connected to outputs of opposite polarity, each half-cell including:
• first and second transistors connected to the outputs and driven by a first voltage;
• third and fourth transistors each connected in series with the first and second transistors respectively, and each driven by a corresponding data signal;
• a first plurality of transistors connected in series with each other and driven by a second voltage,
• wherein a drain of a first transistor of the first plurality of transistors is connected to sources of the third and fourth transistors;
• and
• a second plurality of transistors each connected across a source and drain of one transistor of the first plurality of transistors and driven by a third voltage.