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US 6,720,797 B2Granted
Pass transistor circuit with exclusive controls
AssigneeFujitsu Limited
InventorMitsuru Sasaki
Life of this patent
Estimating the term…
Abstract
A pass transistor circuit comprises a plurality of pass transistors connected in parallel. The same input signal is inputted into the sources of these pass transistors. Continuities of these pass transistors are controlled by a plurality of control signals having an exclusive relationship therebetween. A plurality of buffers respectively drive the drive segments including at least the pass transistors and wirings. The drive segments being a plurality of divided ranges each having an equal potential.
Claims5
A pass transistor circuit comprising:
- a plurality of pass transistors connected in parallel and each one having input terminals and output terminals, wherein the same input signal is being inputted into said input terminals of said pass transistors, and wherein groups of the output terminals of the pass transistors are connected to different nodes, and continuities of the plurality of said pass transistors is being controlled by a plurality of control signals having an exclusive relationship therebetween;
- means for reducing delay differences among the outputs of the plurality of pass transistors connected in parallel;
- and
- a plurality of buffers which drive drive segments including at least said pass transistors and wirings, the drive segments being a plurality of divided ranges each having an equal potential.
1 more element
A pass transistor circuit design method comprising:
- a first step of designing a plurality of pass transistors connected in parallel and having input terminals, respectively, into which input terminals the same input signal is inputted and wherein groups of the output terminals of the pass transistors are connected to different nodes, continuities of the plurality of pass transistors controlled by a plurality of control signals having an exclusive relationship therebetween;
- a second step of designing a plurality of buffers respectively driving drive segments including at least the plurality of pass transistors and wirings, the drive segments being a plurality of divided ranges each having an equal potential;
- and
- a third step of designing a means for reducing delay differences among the outputs of the plurality of pass transistors connected in parallel.
1 more element
Dependencies are inferred from the claim text.