# US 6,720,796 B1 · Multiple size memories in a programmable logic device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 6,720,796 B1
- Document ID: US6720796B1
- Status: Granted
- Kind: B1
- Application number: 10/140,311
- Filed: 2002-05-06
- Granted: 2004-04-13
- Earliest claimed: 2001-05-06
- Assignees: Altera Corporation
- Inventors: Srinivas Reddy; David Jefferson; Christopher F. Lane; Vikram Santurkar; Richard Cliff
- Web page: https://patentgrep.com/patent/US6720796B1

## CPC

- H03K 19/1776: for memories
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

## Claims

### Claim 1

A programmable logic device (PLD) comprising:
an array of logic elements;
a first memory block having a set of control logic and circuits,
wherein the first memory block is disposed within the array of logic elements; and
at least a second memory block having a set of control logic and circuits,
wherein the second memory block is disposed within the array of logic elements, and
wherein the first and second memory blocks have different memory sizes.

### Claim 2 (depends on 1)

The PLD of claim 1, wherein the first memory device is a Random Access Memory.

### Claim 3 (depends on 1)

The PLD of claim 1 further comprising:
a column of the second memory blocks disposed adjacent a column of logic elements,
wherein each of the second memory blocks is connected to a vertical line and a horizontal line.

### Claim 4 (depends on 1)

The PLD of claim 1 further comprising:
a third memory block having a set of control logic and circuits,
wherein the first and third memory blocks have different memory sizes, and
wherein the second and third embedded memory blocks have different memory sizes.

### Claim 5 (depends on 4)

The PLD of claim 4, wherein the first memory block has greater memory size than the second memory block, and wherein the second memory block has greater memory size the third memory block.

### Claim 6 (depends on 4)

The PLD of claim 4 further comprising:
a column of the second memory blocks; and
a column of the third memory blocks.

### Claim 7 (depends on 4)

The PLD of claim 4, wherein each one of the second and third memory blocks is connected to one vertical line and one horizontal line.

### Claim 8

A programmable logic device (PLD) comprising:
an array of logic elements;
a first embedded memory block disposed within the array of logic elements; and
at least a second embedded memory block disposed within the array of logic elements,
wherein the first memory block has greater memory size than the second embedded memory block.

### Claim 9 (depends on 8)

The PLD of claim 8 further comprising:
a third embedded memory block,
wherein the second embedded memory block has greater memory size than the embedded memory block.

### Claim 10 (depends on 9)

The PLD of claim 9, wherein a plurality of the second embedded memory blocks are arranged in a column.

### Claim 11 (depends on 10)

The PLD of claim 10, wherein a plurality of the third embedded memory blocks are arranged in a column.

### Claim 12 (depends on 11)

The PLD of claim 11, wherein the first embedded memory block is a Random Access Memory.

### Claim 13

A method of designing a programmable logic device (PLD), comprising:
designing the PLD such that the PLD includes an array of logic elements;
designing the PLD to embed a first memory block within the array of logic elements; and
designing the PLD to embed a second memory block within the array of logic elements,
wherein the first and second memory blocks each have a set of control logic and circuits, and
wherein the first and second memory blocks have different memory sizes.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
selecting a first memory block having a larger memory size than the second memory block.

### Claim 15 (depends on 14)

The method of claim 14 further comprising:
designing the PLD to embed a third memory block within the array of logic elements,
wherein the third memory block has a set of control logic and circuits, and
wherein the third memory block has a different memory size than the first or second memory block.

### Claim 16 (depends on 15)

The method of claim 15 further comprising:
selecting a third memory block having a smaller memory size than the second memory block.