US 6,720,794 B2Granted

Output buffer circuit

AssigneeOki Electric Industry Co., Ltd.

InventorToshimichi Seike

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Abstract

An output buffer circuit comprises an input terminal, an output terminal first and second inverters, a pull up control circuit, a pull down control circuit and first and second output transistors. Each of the first and second inverters is connected to the input terminal for outputting a signal having a slow rise up and fall down characteristic. Both of the pull up and pull down control circuits are connected to the input terminal and the output terminal. The pull up control circuit pulls up an output voltage of the first inverter when the output signal of the first inverter has a level lower than a first threshold voltage level. The pull up control circuit stops the pull up operation when the level of the output signal of the first inverter exceeds the first threshold voltage level. The pull down control circuit pulls down an output voltage of the second inverter when the output signal of the second inverter has a level higher than a second threshold voltage level. The pull down control circuit stops the pull down operation when the pull down control circuit becomes lower than the second threshold voltage level. The first output transistor has a source connected to a first power source, a drain connected to the output terminal and a gate connected to the first inverter. The second output transistor has a source connected to a second power source, a drain connected to the output terminal and a gate connected to the second inverter.

Claims10

Dependent claims

An output buffer circuit comprising:

an input terminal for receiving an input signal;
an output terminal for outputting an output signal;
a first inverter connected to the input terminal, the first inverter outputting a first signal having a slow rise up and fall down characteristic;
a second inverter connected to the input terminal, the second inverter outputting a second signal having the slow rise up and fall down characteristic;
a pull up control circuit connected to the input terminal and the output terminal, the pull up control circuit pulling up an output voltage of the first signal when the first signal has a level lower than a first threshold voltage level and stopping the pull up of the output voltage of the first signal when the level of the first signal exceeds the first threshold voltage level;
a pull down control circuit connected to the input terminal and the output terminal, the pull down control circuit pulling down an output voltage of the second signal when the second signal has a level higher than a second threshold voltage level and stopping the pull down of the output voltage of the second signal when the level of the second signal becomes lower than the second threshold voltage level;
a first output transistor having a source connected to a first power source potential node, a drain connected to the output terminal and a gate connected to the first inverter so as to receive the first signal;
and
a second output transistor having a source connected to a second power source potential node, a drain connected to the output terminal and a gate connected to the second inverter so as to receive the second signal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/194,297Filed 15 Jul 2002
Priority: JP 2001/21537616 Jul 2001
Published: US 2003/0011402 A116 Jan 2003
Granted: 13 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 17/166
By feedback from the output circuit to the control circuit: soft switching
H03K 19/0013
Arrangements for reducing power consumption: in field effect transistor circuits
H03K 19/09429
Multistate logic: one of the states being the high impedance or floating state
H03K 2217/0018
Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00: special modifications or…