Back to results
US 6,720,793 B1Granted
Quintuple modular redundancy for high reliability circuits implemented in programmable logic devices
AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeXilinx, Inc.
InventorStephen M. Trimberger
Estimating the term…
Structures and methods for generating high reliability designs for PLDs on which single event upsets have minimal impact. When standard triple modular redundancy (TMR) methods are used in PLDS, a single event upset can short together two module output signals and render two of the three voting circuit input signals invalid. The invention addresses this issue by providing quintuple modular redundancy (QMR) for high-reliability circuits implemented in PLDs. Thus, a single event upset that inadvertently shorts together two PLD interconnect lines can render invalid only two out of five module output signals. The majority of the five modules still provide the correct value, and the voting circuit is able to correctly resolve the error. In some embodiments, a user selects a high-reliability circuit implementation option and/or a PLD particularly suited to a QMR implementation, and the PLD implementation software automatically implements the QMR structure for the user circuit.
A structure implementing a user circuit in a programmable logic device (PLD), the PLD including programmable logic blocks, programmable interconnect lines, and programmable interconnect points (PIPs) interconnecting the logic blocks and interconnect lines, the structure comprising:
A method of implementing a user circuit in a programmable logic device (PLD), the PLD including programmable logic blocks, programmable interconnect lines, and programmable interconnect points (PIPs) interconnecting the logic blocks and interconnect lines, the method comprising:
A method of implementing a user circuit in a programmable logic device (PLD), the PLD including programmable logic blocks, programmable interconnect lines, and programmable interconnect points (PIPs) interconnecting the logic blocks and interconnect lines, the method comprising:
Dependencies are inferred from the claim text.