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US 6,720,639 B2Granted
Integrated inductance structure
AssigneeSTMicroelectronics S.r.l.
InventorFrédéric Lemaire
Life of this patent
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Abstract
An integrated circuit inductance structure, including a silicon substrate, a planar winding of a conductive track, a resistive layer, not etched under the winding, a dielectric layer between the winding and said resistive layer, and discontinuous conductive sections, individually parallel to a portion of the winding which is the closest and electrically connected to ground and to the more heavily-doped layer.
Claims8
An integrated circuit inductance structure, including:
- a silicon substrate;
- at least one planar winding of a conductive track;
- a resistive layer, not etched under the winding;
- a dielectric layer between the winding and said resistive layer;
- and
- discontinuous conductive sections, individually parallel to a closest portion of the winding, and electrically connected to ground and to said resistive layer.
3 more elements
Dependencies are inferred from the claim text.