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US 6,720,637 B2Granted
SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks
AssigneeInternational Business Machines Corporation
InventorSteven Howard Voldman
Life of this patent
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Abstract
An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.
Claims8
An SiGe device comprising:
- a semiconductor substrate of a first conductivity type;
- a doped collector region formed on top of said semiconductor substrate, said doped collector region of second conductivity type;
- shallow trench isolation (STI) regions extending into said device to define an extrinsic collector portion of said doped collector region therebetween and defining an intrinsic SiGe base portion of said first conductivity type above said extrinsic collector portion therebetween, and;
- a polysilicon germanium layer forming an extrinsic base region of a first conductivity type overlaying said intrinsic base portion and surfaces of said STI regions,
- wherein said device is configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents.
2 more elements
A Heterojunction Bipolar Transistor (HBT) SiGe device comprising:
- a semiconductor substrate of a first conductivity type;
- a doped collector region formed on top of said semiconductor substrate, said doped collector region of second conductivity type;
- shallow trench isolation (STI) regions extending into said device to define an extrinsic collector portion of said doped collector region therebetween and defining an intrinsic SiGe base portion of said first conductivity type above said extrinsic collector portion therebetween, and;
- a polysilicon germanium layer grown by low temperature epitaxy forming an extrinsic base region of a first conductivity type overlaying said intrinsic SiGe base portion and surfaces of said STI regions, said polysilicon germanium layer including an emitter implant region of said second conductivity type aligned with said intrinsic SiGe base portion,
- a dielectric film formed on said extrinsic base region defining said emitter implant region;
- and,
- a polysilicon germanium layer of said second conductivity type forming an emitter region overlaying said dielectric film and said emitter implant region for contact therewith,
- wherein said HBT SiGe device base region is electrically connected with said emitter region, said collector and base regions forming a base-collector diode, said device being selectively doped to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents.
5 more elements
Dependencies are inferred from the claim text.