US 6,720,633 B2Granted

High withstand voltage insulated gate N-channel field effect transistor

AssigneeSeiko Instruments Inc.

InventorsHirofumi Harada, Jun Osanai

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Abstract

A high withstand voltage insulated gate N-channel field effect transistor has N-type source and drain regions formed on a semiconductor substrate, and a channel forming region disposed between the source and drain regions. A gate insulating film is disposed over the channel forming region. A gate electrode is formed on the channel forming region through the gate insulating film. N-type low concentration regions are formed between respective ones of the drain region and the channel forming region and the source region and the channel forming region. Second insulating films are formed on respective ones of the low concentration regions. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, the gate insulating film, and the second insulating films. A P-type well layer is formed in a part of a region under the gate insulating film.

Claims15

Dependent claims

A high withstand voltage insulated gate N-channel field effect transistor comprising:

a P-type semiconductor substrate;
an N-type epitaxial layer formed on the semiconductor substrate;
an N-type source region having a high concentration formed on the epitaxial layer;
an N-type drain region having a high concentration formed on the epitaxial layer and spaced-apart from the source region;
a channel forming region disposed between the source region and the drain region;
a first insulating film comprised of a gate insulating film disposed over the channel forming region;
a gate electrode formed on the channel forming region through the gate insulating film;
N-type low concentration regions formed between respective ones of the drain region and the channel forming region and the source region and the channel forming region;
a second insulating films each formed on a respective one of the low concentration regions and having a thickness greater than that of the gate insulating film;
a P-type buried layer formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, the gate insulating film, and the second insulating films;
and a P-type well layer formed in a part of a region under the gate insulating film.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/306,696Filed 27 Nov 2002 · continuation
Priority: 22 Jan 1999
Published: US 2003/0080382 A11 May 2003
Granted: 13 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 62/157
Drain regions of DMOS transistors: impurity concentrations or distributions