# US 6,720,631 B2 · Transistor having a deposited dual-layer spacer structure

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- Number: US 6,720,631 B2
- Document ID: US6720631B2
- Status: Granted
- Kind: B2
- Application number: 08/954,430
- Filed: 1997-10-20
- Published: 2001-11-22
- Granted: 2004-04-13
- Earliest claimed: 1995-12-11
- Assignees: Intel Corporation
- Inventors: Lawrence N. Brigham; Raymond E. Cotner; Makarem A. Hussein
- Web page: https://patentgrep.com/patent/US6720631B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/516: {the thicknesses being non-uniform}
- Y10S 257/90: MOSFET type gate sidewall insulating spacer
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.

## Claims

### Claim 1

A transistor comprising:
a gate dielectric disposed over a semiconductor substrate;
a gate electrode disposed over said gate dielectric, said gate electrode having laterally opposed sidewalls;
a pair of tip regions disposed within said semiconductor substrate adjacent to said gate electrode, said pair of tip regions being shallow, heavily doped, and substantially aligned to said sidewalls of said gate electrode;
a pair of spacer structures disposed adjacent to said gate electrode, said pair of spacer structures being deposited and comprising:
a first layer, said first layer covering said sidewalls of said gate electrode and said semiconductor substrate adjacent to said sidewalls; and
a second layer, said second layer covering said first layer; and
a pair of source/drain regions within said semiconductor substrate adjacent to said pair of spacer structures, wherein a supply voltage of less than 5 volts is coupled to said pair of source/drain regions to reduce hot electron charging effects in said gate dielectric to acceptable levels.

### Claim 2 (depends on 1)

The transistor of claim 1 wherein said second layer has a thickness of less than 100 Å.

### Claim 3 (depends on 1)

The transistor of claim 1 wherein said first layer has a thickness of less than 50 Å.

### Claim 4 (depends on 1)

The transistor of claim 1 wherein said first layer has a thickness of 50-300 Å and said second layer has a thickness of less than 500 Å.

### Claim 5 (depends on 1)

The transistor of claim 1 wherein the implant dose used to form said pair of tip regions is at least 0.5 order of magnitude less than the implant dose used to form said pair of source/drain regions.

### Claim 6 (depends on 1)

The transistor of claim 1 wherein said gate dielectric comprises oxide and nitride.

### Claim 7 (depends on 1)

The transistor of claim 1 wherein said gate electrode has a width of less than 0.1 um.

### Claim 8 (depends on 1)

The transistor of claim 1 wherein the lower corners of said gate electrode lie predominantly flat and square with the surface of said semiconductor substrate.

### Claim 9 (depends on 1)

The transistor of claim 1 therein said pair of spacer structures further comprises a third layer.

### Claim 10 (depends on 9)

The transistor of claim 9 wherein said third layer comprises one or more of the following: oxide, nitride, oxynitride, polysilicon, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), organic materials such as polyimide.

### Claim 11 (depends on 9)

The transistor of claim 9 wherein said third layer is disposed below said first layer.

### Claim 12 (depends on 9)

The transistor of claim 9 wherein said third layer is disposed above said second layer.

### Claim 13 (depends on 1)

The transistor of claim 1 wherein said pair of spacer structures separates suicide regions disposed over said gate electrode and over said source/drain regions.

### Claim 14 (depends on 1)

The transistor of claim 1 further comprising:
a second gate dielectric disposed over said gate electrode, and
a second gate electrode disposed over said second gate dielectric.

### Claim 15

A transistor comprising:
a gate dielectric disposed over a semiconductor substrate;
a gate electrode disposed over said gate dielectric;
a pair of heavily-doped (n+) tip regions disposed within said semiconductor substrate adjacent to said gate electrode;
a pair of deposited spacer structures disposed over said pair of heavily-doped (n+) tip regions; and
a pair of source/drain regions disposed within said semiconductor substrate adjacent to said pair of heavily-doped (n+) tip regions, said tip regions being extensions of said source/drain regions.

### Claim 16 (depends on 15)

The transistor of claim 15 wherein the pair of deposited spacer structures comprises oxide with a thickness of less than 50 Å and nitride with a thickness of less than 500 Å.