Semiconductor device having junction depths for reducing short channel effect

A CMOS-type semiconductor device comprising:

• an NMOSFET and a PMOSFET,
• wherein n-type source and drain regions of the NMOSFET have a greater junction depth than P-type source and drain regions of the PMOSFET,
• the NMOSFET and the PMOSFET each have gate electrodes,
• silicide films are formed on the n-type source and drain regions and the p-type source and drain regions, or on the n-type source and drain regions, the p-type source and drain regions and the gate electrodes, and
• the silicide films in the NMOSFET and PMOSFET are almost equal in thickness, wherein each of the sidewall spacers has a lateral thickness of at least about 0.7 multiplied by the junction depth of a corresponding source and drain regions.

A CMOS-type semiconductor device comprising:

• an NMOSFET and a PMOSFET,
• wherein n-type source and drain regions of the NMOSFET have a greater junction depth than P-type source and drain regions of the PMOSFET,
• the NMOSFET and the PMOSFET each have gate electrodes,
• silicide films are formed on the n-type source and drain regions and the p-type source and drain regions, or on the n-type source and drain regions, the p-type source and drain regions and the gate electrodes, and
• the suicide films in the NMOSFET and PMOSFET are almost equal in thickness, wherein
• each of the sidewall spacers has a lateral thickness within the range of about 0.7 to 1.2,
• multiplied by the junction depth of the corresponding source and drain regions.