Operation method for programming and erasing a data in a P-channel sonos memory cell

An operation method for programming and erasing a data in a P-channel silicon-ONO-silicon (SONOS) memory cell, wherein the SONOS memory cell comprises a substrate, an ONO layer on the substrate, a gate electrode layer, and two doped regions in the substrate at each side of the ONO layer, the operation method comprising:

• assigning a drain region and a source region to the two doped regions;
• locally trapping hot holes into the ONO layer at a first bit region near the drain region when a programming action is intended;
• and
• driving hot electrons locally to the ONO layer near the drain region, whereby the hot holes are annihilated away when an erasing action is intended, wherein the step of driving hot electrons locally to the ONO layer comprises a bias setting configuration that the drain region is set to a first negative voltage level, the gate electrode is set to a second negative voltage level, and the substrate is set to a grounded voltage, wherein the first negative voltage level is larger in absolute value than the second negative voltage level, and wherein a difference between the first negative voltage level and the second negative voltage level is sufficient to generate the hot electrons and drive the hot electrons into the ONO layer.

A method for programming and erasing a data on a P-channel silicon-ONO-silicon (SONOS) memory cell, wherein the SONOS memory cell comprises a substrate, an ONO layer on the substrate, a gate electrode layer, and two doped regions in the substrate at each side of the ONO layer, the operation method comprising:

• assigning one of the two doped regions to be a source region and then another one of the two doped regions to be a drain region;
• programming the memory cell at a first bit region near the drain region by applying a first bias configuration to the gate electrode, the drain region, the source region, and the substrate, whereby hot holes are driven into the ONO layer, wherein the first bias configuration in the step of programming the memory cell comprises setting the gate electrode and the drain region to be a first negative voltage level, and setting the source region and the substrate to a grounded voltage, wherein the first negative voltage level is sufficient to generate the hot electrons and drive the hot electrons into the ONO layer;
• and
• driving hot electrons locally into the first bit of the ONO layer by applying a second bias configuration to the gate electrode, the drain region, the source region, and the substrate, whereby the hot holes at the first bit region are annihilated away when an erasing action is intended.

A method for programming and erasing a data on a P-channel silicon-ONO-silicon (SONOS) memory cell, wherein the SONOS memory cell comprises a substrate, an ONO layer on the substrate, a gate electrode layer, and two doped regions in the substrate at each side of the ONO layer, the operation method comprising:

• assigning one of the two doped regions to be a source region and then another one of the two doped regions to be a drain region;
• programming the memory cell at a first bit region near the drain region by applying a first bias configuration to the gate electrode, the drain region, the source region, and the substrate, whereby hot holes are driven into the ONO layer;
• and
• driving hot electrons locally into the first bit of the ONO layer by applying a second bias configuration to the gate electrode, the drain region, the source region, and the substrate, whereby the hot holes at the first bit region are annihilated away when an erasing action is intended, wherein the second bias configuration in the step of driving hot electrons locally into the first bit region of the ONO layer comprises setting the drain region is set to a first negative voltage level, setting the gate electrode to a second negative voltage level, and setting the substrate to a grounded voltage, wherein the first negative voltage level is larger in absolute value than the second negative voltage level, and a difference between the first negative voltage level and the second negative voltage level is sufficient to generate the hot electrons and drive the hot electrons into the ONO layer.