# US 6,720,605 B1 · Aluminum-filled self-aligned trench for stacked capacitor structure and methods

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- Number: US 6,720,605 B1
- Document ID: US6720605B1
- Status: Granted
- Kind: B1
- Application number: 09/651,879
- Filed: 2000-08-29
- Granted: 2004-04-13
- Earliest claimed: 1998-06-22
- Assignees: Micron Technology, Inc.
- Inventors: Ruojia Lee; Ralph Kauffman; J. Dennis Keller
- Web page: https://patentgrep.com/patent/US6720605B1

## CPC

- H10B 12/485: {Bit line contacts}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/716: {having vertical extensions}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10B 12/312: {with a bit line higher than the capacitor}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a semiconductor substrate including at least one active device region;
a stacked capacitor structure disposed above said semiconductor substrate, including a portion that extends substantially over at least one transistor gate and includes at least one oxidized lateral edge that extends substantially to an edge of an interconnect location and is in electrical isolation from said interconnect location; and
a first interconnect element comprising aluminum extending adjacent said at least one lateral edge of said stacked capacitor structure and in electrical communication with said at least one active device region through a second interconnect element comprising a metal silicide, said at least one active device region being substantially covered by said second interconnect element and at least a side wall spacer of said transistor gate; and
at least one bit line formed from the same aluminum-comprising material as said first interconnect element and extending over said stacked capacitor structure, said at least one bit line and said first interconnect element comprising a unitary structure with no discernable boundary being located between said first interconnect element and said at least one bit line.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein said first interconnect element is disposed within a contact aperture adjacent said at least one transistor gate.

### Claim 3 (depends on 1)

The semiconductor device structure of claim 1, further comprising a buried metal diffusion layer adjacent said at least one active device region.

### Claim 4 (depends on 3)

The semiconductor device structure of claim 3, wherein said buried metal diffusion layer comprises a metal silicide.

### Claim 5 (depends on 4)

The semiconductor device structure of claim 4, wherein said metal silicide is selected from titanium suicide and tungsten silicide.

### Claim 6 (depends on 5)

The semiconductor device structure of claim 5, wherein said buried metal diffusion layer further comprises a metal nitride layer adjacent said metal silicide.

### Claim 7 (depends on 1)

The semiconductor device structure of claim 1, further comprising a metal silicide layer disposed above said at least one active device region.

### Claim 8 (depends on 7)

The semiconductor device structure of claim 7, wherein said metal silicide is selected from titanium silicide layer and tungsten silicide.

### Claim 9 (depends on 7)

The semiconductor device structure of claim 7, further comprising a metal nitride adjacent said metal silicide layer.

### Claim 10 (depends on 9)

The semiconductor device structure of claim 9, wherein said metal nitride comprises titanium nitride or tungsten nitride.

### Claim 11 (depends on 9)

The semiconductor device structure of claim 9, wherein said metal nitride contacts said first interconnect element.

### Claim 12 (depends on 9)

The semiconductor device structure of claim 9, wherein said metal nitride is disposed between said metal silicide layer and said first interconnect element.

### Claim 13 (depends on 1)

The semiconductor device structure of claim 1, wherein said first interconnect element extends through said stacked capacitor structure.

### Claim 14 (depends on 1)

The semiconductor device structure of claim 1, wherein said first interconnect element is electrically insulated from said stacked capacitor structure.

### Claim 15 (depends on 1)

The semiconductor device structure of claim 1, wherein said at least one active device region comprises a source or a drain.

### Claim 16 (depends on 1)

The semiconductor device structure of claim 1, wherein said first interconnect element has a contact resistance of less than about 5 μΩ-cm.