Capacitor structure and a semiconductor device with a first metal layer, a second metal silicide layer formed over the first metal layer and a second metal layer formed over the second metal silicide layer

A semiconductor integrated circuit device having a capacitor of a DRAM comprising:

• a memory cell selecting MISFET of the DRAM, including a source region, a drain region, and a gate electrode;
• a silicon plug electrically connected to the source region or the drain region;
• a lower metal electrode of the capacitor electrically connected to the silicon plug;
• a dielectric film of the capacitor formed over the lower metal electrode;
• and
• an upper metal electrode formed over the dielectric film;
• wherein a first metal silicide layer is formed on the surface of the silicon plug;
• a metal silicon nitrid layer or a metal silicon oxynitride layer is formed on the surface of the first metal silicide layer;
• and
• the lower metal electrode further comprises a first metal layer, an oxide-absorption layer formed over the first metal layer, and a second metal layer formed over the oxide-absorption layer.

A semiconductor integrated circuit device having a capacitor of a DRAM comprising:

• a memory cell selecting MISFET of the DRAM, including a source region, a drain region, and a gate electrode;
• a silicon plug electrically connected to the source region or the drain region;
• an interlayer insulating layer formed over the silicon plug;
• a groove formed in the interlayer insulating layer;
• a lower metal electrode of the capacitor formed inside the groove, which is electrically connected to the silicon plug;
• a dielectric film of the capacitor formed over the lower metal electrode;
• and
• an upper metal electrode formed over the dielectric film;
• wherein the lower metal electrode of the capacitor is formed over an inner side surface and a bottom surface of the groove;
• and
• a silicide layer is formed between the bottom surface of the groove and the lower metal electrode;
• and
• the silicide layer is formed between the inner side surface of the groove and the lower metal electrode.